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| hitachi single-chip microcomputer h8/338 series h8/338 hd6473388, hd6433388, hd6413388 h8/337 hd6473378, hd6433378, hd6413378 h8/336 hd6433368 hardware manual ade-602-039b rev. 3.0 september 21, 1998 hitachi company or division
cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachis or any third partys patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third partys rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachis sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachis sales office for any questions regarding this document or hitachi semiconductor products. rev. 3.0, 09/98, page i of viii preface the h8/338 series is a series of high-performance single-chip microcomputers having a fast h8/300 cpu core and a set of on-chip supporting functions optimized for embedded control. these include rom, ram, three types of timers, a serial communication interface, an a/d converter, a d/a converter, i/o ports, and other functions needed in control system configurations, so that compact, high-performance systems can be realized easily. the h8/338 series includes three chips: the h8/338 with 48k-byte rom and 2k-byte ram; the h8/337 with 32k-byte rom and 1k-byte ram; and the h8/336 with 24k-byte rom and 1k-byte ram. the h8/338 and h8/337 are available in a masked rom version, a ztat ? *(zero turn-around time) version, and a romless version, providing a quick and flexible response to conditions from ramp-up through full-scale volume producion, even for applications with frequently-changing specifications. this manual describes the hardware of the h8/338 series. refer to the h8/300 series programming manual for a detailed description of the instruction set. note: ztat is a registered trademark of hitachi, ltd. rev. 3.0, 09/98, page ii of viii contents section 1 overview .......................................................................................................... 1 1.1 overview .................................................................................................................... ...... 1 1.2 block diagram............................................................................................................... ... 4 1.3 pin assignments and functions........................................................................................ 5 1.3.1 pin arrangement.................................................................................................. 5 1.3.2 pin functions ....................................................................................................... 8 section 2 cpu .................................................................................................................... 15 2.1 overview .................................................................................................................... ...... 15 2.1.1 features................................................................................................................ 15 2.2 register configuration...................................................................................................... 16 2.2.1 general registers................................................................................................. 17 2.2.2 control registers ................................................................................................. 17 2.2.3 initial register values ......................................................................................... 18 2.3 addressing modes ............................................................................................................ 19 2.3.1 addressing modes ............................................................................................... 19 2.3.2 how to calculate where the excution starts ...................................................... 21 2.4 data formats................................................................................................................ ..... 25 2.4.1 data formats in general registers ...................................................................... 26 2.4.2 memory data formats......................................................................................... 27 2.5 instruction set............................................................................................................. ...... 28 2.5.1 data transfer instructions ................................................................................... 30 2.5.2 arithmetic operations ......................................................................................... 32 2.5.3 logic operations ................................................................................................. 33 2.5.4 shift operations................................................................................................... 33 2.5.5 bit manipulations ................................................................................................ 35 2.5.6 branching instructions......................................................................................... 39 2.5.7 system control instructions ................................................................................ 41 2.5.8 block data transfer instruction .......................................................................... 42 2.6 cpu states.................................................................................................................. ...... 44 2.6.1 program execution state ..................................................................................... 45 2.6.2 exception-handling state.................................................................................... 45 2.6.3 power-down state............................................................................................... 46 2.7 access timing and bus cycle .......................................................................................... 47 2.7.1 access to on-chip memory (ram and rom)................................................... 47 2.7.2 access to on-chip register field and external devices .................................... 49 section 3 mcu operating modes and address space .......................................... 53 3.1 overview .................................................................................................................... ...... 53 rev. 3.0, 09/98, page iii of viii 3.1.1 mode selection.................................................................................................... 53 3.1.2 mode and system control registers (mdcr and syscr)................................ 54 3.2 system control register (syscr) ? h'ffc4 .................................................................. 54 3.3 mode control register (mdcr) ? h'ffc5...................................................................... 56 3.4 address space map .......................................................................................................... 5 7 section 4 exception handling ....................................................................................... 61 4.1 overview .................................................................................................................... ...... 61 4.2 reset ....................................................................................................................... .......... 61 4.2.1 overview ............................................................................................................. 61 4.2.2 reset sequence .................................................................................................... 61 4.2.3 disabling of interrupts after reset....................................................................... 64 4.3 interrupts.................................................................................................................. ......... 64 4.3.1 overview ............................................................................................................. 64 4.3.2 interrupt-related registers.................................................................................. 66 4.3.3 external interrupts ............................................................................................... 68 4.3.4 internal interrupts ................................................................................................ 68 4.3.5 interrupt handling ............................................................................................... 68 4.3.6 interrupt response time ..................................................................................... 74 4.3.7 precaution ............................................................................................................ 75 4.4 note on stack handling.................................................................................................... 76 section 5 clock pulse generator .................................................................................. 77 5.1 overview .................................................................................................................... ...... 77 5.1.1 block diagram..................................................................................................... 77 5.2 oscillator circuit .......................................................................................................... .... 78 5.3 system clock divider....................................................................................................... 8 0 section 6 i/o ports ............................................................................................................ 81 6.1 overview .................................................................................................................... ...... 81 6.2 port 1 ...................................................................................................................... .......... 84 6.3 port 2 ...................................................................................................................... .......... 88 6.4 port 3 ...................................................................................................................... .......... 92 6.5 port 4 ...................................................................................................................... .......... 96 6.6 port 5 ...................................................................................................................... .......... 100 6.7 port 6 ...................................................................................................................... .......... 105 6.8 port 7 ...................................................................................................................... .......... 111 6.9 port 8 ...................................................................................................................... .......... 113 6.10 port 9 ..................................................................................................................... ........... 119 section 7 16-bit free-running timer ........................................................................ 127 7.1 overview .................................................................................................................... ...... 127 7.1.1 features................................................................................................................ 12 7 rev. 3.0, 09/98, page iv of viii 7.1.2 block diagram..................................................................................................... 127 7.1.3 input and output pins .......................................................................................... 129 7.1.4 register configuration ........................................................................................ 129 7.2 register descriptions....................................................................................................... .130 7.2.1 free-running counter (frc) ? h'ff92 .............................................................. 130 7.2.2 output compare registers a and b (ocra and ocrb) ? h'ff94 ................... 131 7.2.3 input capture registers a to d (icra to icrd) ? h'ff98, h'ff9a, h'ff9c, h'ff9e ..................................................................... 131 7.2.4 timer interrupt enable register (tier) ? h'ff90.............................................. 134 7.2.5 timer control/status register (tcsr) ? h'ff91................................................ 136 7.2.6 timer control register (tcr) ? h'ff96............................................................. 139 7.2.7 timer output compare control register (tocr) ? h'ff97 .............................. 141 7.3 cpu interface ............................................................................................................... .... 143 7.4 operation ................................................................................................................... ....... 146 7.4.1 frc incrementation timing................................................................................ 146 7.4.2 output compare timing...................................................................................... 148 7.4.3 input capture timing .......................................................................................... 149 7.4.4 setting of frc overflow flag (ovf) ................................................................. 152 7.5 interrupts.................................................................................................................. ......... 152 7.6 sample application .......................................................................................................... 153 7.7 application notes ........................................................................................................... .. 154 section 8 8-bit timers .................................................................................................... 159 8.1 overview .................................................................................................................... ...... 159 8.1.1 features................................................................................................................ 15 9 8.1.2 block diagram..................................................................................................... 160 8.1.3 input and output pins .......................................................................................... 161 8.1.4 register configuration ........................................................................................ 161 8.2 register descriptions....................................................................................................... .162 8.2.1 timer counter (tcnt) ? h'ffcc (tmr0), h'ffd4 (tmr1) ........................... 162 8.2.2 time constant registers a and b (tcora and tcorb) ? h'ffca and h'ffcb (tmr0), h'ffd2 and h'ffd3 (tmr1)........................... 162 8.2.3 timer control register (tcr) ? h'ffc8 (tmr0), h'ffd0 (tmr1)................. 163 8.2.4 timer control/status register (tcsr) ? h'ffc9 (tmr0), h'ffd1 (tmr1).... 166 8.2.5 serial/timer control register (stcr) ? h'ffc3 ............................................... 168 8.3 operation ................................................................................................................... ....... 169 8.3.1 tcnt incrementation timing............................................................................. 169 8.3.2 compare match timing....................................................................................... 170 8.3.3 external reset of tcnt ...................................................................................... 172 8.3.4 setting of tcsr overflow flag (ovf)............................................................... 172 8.4 interrupts.................................................................................................................. ......... 173 8.5 sample application .......................................................................................................... 173 8.6 application notes ........................................................................................................... .. 174 rev. 3.0, 09/98, page v of viii section 9 pwm timers ................................................................................................... 179 9.1 overview .................................................................................................................... ...... 179 9.1.1 features................................................................................................................ 17 9 9.1.2 block diagram..................................................................................................... 180 9.1.3 input and output pins .......................................................................................... 181 9.1.4 register configuration ........................................................................................ 181 9.2 register descriptions....................................................................................................... .181 9.2.1 timer counter (tcnt) ? h'ffa2 (pwm0), h'ffa6 (pwm1).......................... 181 9.2.2 duty register (dtr) ? h'ffa1 (pwm0), h'ffa5 (pwm1) ............................. 182 9.2.3 timer control register (tcr) ? h'ffa0 (pwm0), h'ffa4 (pwm1)............... 182 9.3 operation ................................................................................................................... ....... 184 9.3.1 timer incrementation .......................................................................................... 184 9.3.2 pwm operation................................................................................................... 185 9.4 application notes ........................................................................................................... .. 186 section 10 serial communication interface ................................................................ 187 10.1 overview ................................................................................................................... ....... 187 10.1.1 features................................................................................................................ 1 87 10.1.2 block diagram..................................................................................................... 188 10.1.3 input and output pins .......................................................................................... 188 10.1.4 register configuration ........................................................................................ 189 10.2 register descriptions...................................................................................................... .. 190 10.2.1 receive shift register (rsr) .............................................................................. 190 10.2.2 receive data register (rdr) ? h'ffdd, h'ff8d ............................................. 190 10.2.3 transmit shift register (tsr)............................................................................. 190 10.2.4 transmit data register (tdr) ? h'ffdb, h'ff8b ............................................ 191 10.2.5 serial mode register (smr) ? h'ffd8, h'ff88 ................................................ 191 10.2.6 serial control register (scr) ? h'ffda, h'ff8a............................................. 194 10.2.7 serial status register (ssr) ? h'ffdc, h'ff8c ................................................ 197 10.2.8 bit rate register (brr) ? h'ffd9, h'ff89 ....................................................... 200 10.2.9 serial/timer control register (stcr) ? h'ffc3 ............................................... 204 10.3 operation .................................................................................................................. ........ 205 10.3.1 overview ............................................................................................................. 205 10.3.2 asynchronous mode............................................................................................ 207 10.3.3 synchronous mode .............................................................................................. 218 10.4 interrupts................................................................................................................. .......... 224 10.5 application notes .......................................................................................................... ... 224 section 11 a/d converter ................................................................................................. 227 11.1 overview ................................................................................................................... ....... 227 11.1.1 features................................................................................................................ 2 27 11.1.2 block diagram..................................................................................................... 228 11.1.3 input pins............................................................................................................. 22 9 rev. 3.0, 09/98, page vi of viii 11.1.4 register configuration ........................................................................................ 229 11.2 register descriptions...................................................................................................... .. 230 11.2.1 a/d data registers (addr) ? h'ffe0 to h'ffe6 ............................................. 230 11.2.2 a/d control/status register (adcsr) ? h'ffe8............................................... 230 11.2.3 a/d control register (adcr) ? h'ffea........................................................... 233 11.3 operation .................................................................................................................. ........ 234 11.3.1 single mode (scan = 0) .................................................................................... 234 11.3.2 scan mode (scan = 1)....................................................................................... 237 11.3.3 input sampling time and a/d conversion time................................................ 239 11.3.4 external trigger input timing............................................................................. 241 11.4 interrupts................................................................................................................. .......... 242 section 12 d/a converter ................................................................................................. 243 12.1 overview ................................................................................................................... ....... 243 12.1.1 features................................................................................................................ 2 43 12.1.2 block diagram..................................................................................................... 244 12.1.3 input and output pins .......................................................................................... 245 12.1.4 register configuration ........................................................................................ 245 12.2 register descriptions...................................................................................................... .. 246 12.2.1 d/a data registers 0 and 1 (dadr0, dadr1) h'ffa8, h'ffa9 .................... 246 12.2.2 d/a control register (dacr) h'ffaa ............................................................. 246 12.3 operation .................................................................................................................. ........ 248 section 13 ram .................................................................................................................. 249 13.1 overview ................................................................................................................... ....... 249 13.2 block diagram.............................................................................................................. .... 249 13.3 ram enable bit (rame) in system control register (syscr).................................... 250 13.4 operation .................................................................................................................. ........ 250 13.4.1 expanded modes (modes 1 and 2) ...................................................................... 250 13.4.2 single-chip mode (mode 3)................................................................................ 250 section 14 rom .................................................................................................................. 251 14.1 overview ................................................................................................................... ....... 251 14.1.1 block diagram..................................................................................................... 252 14.2 prom mode (h8/338, h8/337) ....................................................................................... 252 14.2.1 prom mode setup ............................................................................................. 252 14.2.2 socket adapter pin assignments and memory map........................................... 253 14.3 programming ................................................................................................................ .... 257 14.3.1 writing and verifying ......................................................................................... 257 14.3.2 notes on writing ................................................................................................. 261 14.3.3 reliability of written data .................................................................................. 262 14.3.4 erasing of data .................................................................................................... 263 14.4 handling of windowed packages..................................................................................... 263 rev. 3.0, 09/98, page vii of viii section 15 power-down state ......................................................................................... 265 15.1 overview ................................................................................................................... ....... 265 15.2 system control register: power-down control bits ....................................................... 266 15.3 sleep mode ................................................................................................................. ...... 268 15.3.1 transition to sleep mode..................................................................................... 268 15.3.2 exit from sleep mode.......................................................................................... 268 15.4 software standby mode ................................................................................................... 269 15.4.1 transition to software standby mode ................................................................. 269 15.4.2 exit from software standby mode ...................................................................... 269 15.4.3 sample application of software standby mode ................................................. 270 15.4.4 application note.................................................................................................. 271 15.5 hardware standby mode .................................................................................................. 272 15.5.1 transition to hardware standby mode................................................................ 272 15.5.2 recovery from hardware standby mode ............................................................ 272 15.5.3 timing relationships........................................................................................... 272 section 16 electrical specifications ............................................................................... 275 16.1 absolute maximum ratings ............................................................................................. 275 16.2 electrical characteristics ................................................................................................. .275 16.2.1 dc characteristics............................................................................................... 275 16.2.2 ac characteristics............................................................................................... 281 16.2.3 a/d converter characteristics............................................................................. 286 16.2.4 d/a converter characteristics............................................................................. 287 16.3 mcu operational timing................................................................................................. 287 16.3.1 bus timing .......................................................................................................... 288 16.3.2 control signal timing ......................................................................................... 290 16.3.3 16-bit free-running timer timing .................................................................... 292 16.3.4 8-bit timer timing ............................................................................................. 293 16.3.5 pulse width modulation timer timing............................................................... 294 16.3.6 serial communication interface timing ............................................................. 294 16.3.7 i/o port timing ................................................................................................... 295 appendix a cpu instruction set ................................................................................... 297 a.1 instruction set list........................................................................................................ .... 297 a.2 operation code map......................................................................................................... 3 05 a.3 number of states required for execution ........................................................................ 307 appendix b register field ............................................................................................... 313 b.1 register addresses and bit names ................................................................................... 313 b.2 register descriptions....................................................................................................... .317 rev. 3.0, 09/98, page viii of viii appendix c pin states ....................................................................................................... 356 c.1 pin states in each mode ................................................................................................... 35 6 appendix d timing of transition to and recovery from hardware standby mode .......................................................................... 358 appendix e package dimensions .................................................................................. 359 rev. 3.0, 09/98, page 1 of 361 section 1 overview 1.1 overview the h8/338 series of single-chip microcomputers features an h8/300 cpu core and a complement of on-chip supporting modules implementing a variety of system functions. the h8/300 cpu is a high-speed processor with an architecture featuring powerful bit- manipulation instructions, ideally suited for realtime control applications. the on-chip supporting modules implement peripheral functions needed in system configurations. these include rom, ram, three types of timers (16-bit free-running timer, 8-bit timers, pulse-width modulation timers), a serial communication interface (sci), an a/d converter, a d/a converter, and i/o ports. the h8/338 series can operate in a single-chip mode or in two expanded modes, depending on the requirements of the application. (the operating mode will be referred to as the mcu mode in this manual.) the entire h8/338 series is available with masked rom. the h8/338 and h8/337 are also available in ztat ? versions* that can be programmed at the user site, and in romless versions. note: ztat is a registered trademark of hitachi, ltd. table 1.1 lists the features of the h8/338 series. rev. 3.0, 09/98, page 2 of 361 table 1.1 features item specification cpu two-way general register configuration eight 16-bit registers, or sixteen 8-bit registers high-speed operation maximum clock rate: 10mhz add/subtract: 0.2s multiply/divide: 1.4s streamlined, concise instruction set instruction length: 2 or 4 bytes register-register arithmetic and logic operations mov instruction for data transfer between registers and memory instruction set features multiply instruction (8 bits 8 bits) divide instruction (16 bits ? 8 bits) bit-accumulator instructions register-indirect specification of bit positions memory h8/338: 48k-byte rom; 2k-byte ram h8/337: 32k-byte rom; 1k-byte ram h8/336: 24k-byte rom; 1k-byte ram 16-bit free- running timer (1 channel) one 16-bit free-running counter (can also count external events) two output-compare lines four input capture lines (can be buffered) 8-bit timer (2 channels) each channel has one 8-bit up-counter (can also count external events) two time constant registers pwm timer (2 channels) duty cycle can be set from 0 to 100% resolution: 1/250 serial communication interface (sci) (2 channels) asynchronous or clocked synchronous mode (selectable) full duplex: can transmit and receive simultaneously on-chip baud rate generator rev. 3.0, 09/98, page 3 of 361 table 1.1 features (cont) item specification a/d converter 8-bit resolution eight channels: single or scan mode (selectable) start of a/d conversion can be externally triggered sample-and-hold function d/a converter 8-bit resolution two channels i/o ports 58 input/output lines (16 of which can drive leds) 8 input-only lines interrupts nine external interrupt lines: nmi, irq 0 to irq 7 22 on-chip interrupt sources operating modes expanded mode with on-chip rom disabled (mode 1) expanded mode with on-chip rom enabled (mode 2) single-chip mode (mode 3) power-down modes sleep mode software standby mode hardware standby mode other features on-chip oscillator series lineup 5-v version 3-v version package rom hd6473388cg hd6473388f hd6473388vcg hd6473388vf 84-pin windowed lcc (cg-84) 80-pin qfp (fp-80a) prom hd6433388cp hd6433388f hd6433388vcp hd6433388vf 84-pin plcc (cp-84) 80-pin qfp (fp-80a) masked rom hd6413388f hd6413388vf 80-pin qfp (fp-80a) romless hd6473378cg hd6473378f hd6473378vcg hd6473378vf 84-pin windowed lcc (cg-84) 80-pin qfp (fp-80a) prom hd6433378cp hd6433378f hd6433378vcp hd6433378vf 84-pin plcc (cp-84) 80-pin qfp (fp-80a) masked rom HD6413378F hd6413378vf 80-pin qfp (fp-80a) romless hd6433368cp hd6433368f hd6433368vcp hd6433368vf 84-pin plcc (cp-84) 80-pin qfp (fp-80a) masked rom rev. 3.0, 09/98, page 4 of 361 1.2 block diagram figure 1.1 shows a block diagram of the h8/338 series. port 4 port 7 port 5 port 8 port 3 port 9 port 6 cpu h8/300 clock pulse gener- ator ram 16 -bit free- running timer prom (or masked rom) serial communication (2 channels) 8-bit d/a converter (8 channels) 8-bit timer (2 channels) pwm timer (2 channels) p20 /a8 p21 /a9 p2 2 /a10 p2 3 /a11 p2 4 /a12 p2 5 /a13 p2 6 /a14 p2 7 /a15 p70/an0 p71/an1 p72/an2 p73/an3 p74/an4 p75/an5 p76/an6/da0 p77 /an7/da1 av cc av ss p60/ftci p61/ftoa p62 /ftia p63 /ftib p64/ftic p65 /ftid p66/ftob/irq6 p67 /irq7 p52 /sck0 p51 /rxd0 p50 /txd0 p86/sck1/irq5 p85/rxd1/irq4 p84/txd1/irq3 p83 p82 p81 p80 p37/d7 p36/d6 p35/d5 p34/d4 p33/d3 p32/d2 p31/d1 p30/d0 p40/tmci0 p41/tmo0 p42/tmri0 p43/tmci1 p44/tmo1 p45/tmri1 p46/pw0 p47/pw1 p10/a0 port 1 port 2 p11/a1 p12/a2 p13/a3 p14/a4 p15/a5 p16/a6 p17/a7 res md0 md1 vcc stby nmi vcc vss vss vss vss vss vss vss xtal extal p97/wait p96/? p95/as p94/wr p93/rd p92/irq0 p91/irq1 0/adtrg p9 /irq2 * 1 *2 notes: memory sizes h8/338 48k bytes 2k bytes h8/337 32k bytes 1k byte h8/336 24k bytes 1k byte rom ram 1. cp-84 and cg-84 only. 2. prom is available in the h8/338 and h8/337 only. data bus (low) 8-bit d/a converter (2 channels) data (high) address bus figure 1.1 block diagram rev. 3.0, 09/98, page 5 of 361 1.3 pin assignments and functions 1.3.1 pin arrangement figure 1.2 shows the pin arrangement of the cg-84 package. figure 1.3 shows the pin arrangement of the cp-84 package. figure 1.4 shows the pin arrangement of the fp-80a package. 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 11 33 res xtal extal md 1 md 0 nmi stby vcc p5 2 /sck 0 p5 1 /rxd 0 p5 0 /txd 0 vss vss p97/wait p9 6 /? p9 5 /as p9 4 /wr p9 3 /rd p9 2 /irq 0 p9 1 /irq 1 p9 0 /irq 2 /adtrg p1 4 /a 4 p1 5 /a 5 p1 6 /a 6 p1 7 /a 7 vss p2 0 /a 8 p2 1 /a 9 p2 2 /a1 0 p2 3 /a1 1 p2 4 /a1 2 vss p2 6 /a1 4 p2 7 /a1 5 vcc p4 7 /pw 1 p4 6 /pw 0 p4 5 /tmri 1 p4 4 /tmo 1 p4 3 /tmci 1 p4 2 /tmri 0 p8 6 /sck 1 /irq 5 p8 5 /rxd 1 /irq 4 p8 4 /txd 1 /irq 3 p8 3 p8 2 p8 1 p8 0 vss p3 7 /d 7 vss p3 6 /d 6 p3 5 /d 5 p3 4 /d 4 p3 3 /d 3 p3 2 /d 2 p3 1 /d 1 p3 0 /d 0 p1 0 /a 0 p1 1 /a 1 p1 2 /a 2 p1 3 /a 3 p6 0 /ftci p6 1 /ftoa p6 2 /ftia p6 3 /ftib p6 4 /ftic p6 5 /ftid p6 6 /ftob/irq 6 p6 7 /irq 7 vss avcc p70/an0 p71/an1 p72/an2 p73/an3 p74/an4 p75/an5 p76/an6/da0 p77/an7/da1 av ss p40/tmci 0 p41/tmo 0 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 p2 5 /a1 3 figure 1.2 pin arrangement (cg-84, top view) rev. 3.0, 09/98, page 6 of 361 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 11 33 res xtal extal md1 md0 nmi stby vcc p52/sck0 p51/rxd0 p50/txd0 vss vss p97/wait p96/? p95/as p94/wr p93/rd p92/irq0 p91/irq1 p90/irq2/adtrg p14/a4 p15/a5 p16/a6 p17/a7 vss p20/a8 p21/a9 p22/a10 p23/a11 p24/a12 p25 /a13 vss p26 /a14 p27 /a15 vcc p47/pw1 p46/pw0 p45/tmri1 p44/tmo1 p43/tmci1 p42/tmri0 p86/sck1/irq5 p85/rxd1/irq4 p84/txd1/irq3 p83 p82 p81 p80 vss p37/d7 vss p36/d6 p35/d5 p34/d4 p33/d3 p32/d2 p31/d1 p30/d0 p10/a0 p11/a1 p12/a2 p13/a3 p60 /ftci p61/ftoa p62 /ftia p63 /ftib p64 /ftic p65 /ftid p66/ftob/irq6 p67/irq7 vss av cc p70/an0 p71/an1 p72/an2 p73/an3 p74/an4 p75/an5 p76/an6/da0 p77/an7/da1 av ss p40/tmci0 p41/tmo0 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 figure 1.3 pin arrangement (cp-84, top view) rev. 3.0, 09/98, page 7 of 361 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 res xtal extal md1 md0 nmi stby vcc p52/sck0 p51/rxd0 p5 0 /txd0 vss p97/wait p96/? p95/as p94/wr p93/rd p92/irq0 p91/irq1 p90/adtrg/irq2 p14 /a4 p15 /a5 p16 /a6 p17 /a7 vss p20/a8 p21/a9 p22/a10 p23/a11 p24/a12 p25/a13 p26/a14 p27/a15 vcc p47/pw1 p46/pw0 p45/tmri1 p44/tmo1 p43/tmci1 p42/tmri0 p86/sck1/irq5 p85/rxd1/irq4 p84/txd1/irq3 p83 p82 p81 p80 vss p37/d7 p36/d6 p35/d5 p34/d4 p33/d3 p32/d2 p31/d1 p30/d0 p10/a0 p11/a1 p12/a2 p13/a3 p60/ftci p61/ftoa p62/ftia p63/ftib p64/ftic p65/ftid p66/ftob/irq6 p6 7/irq7 av cc p70/an0 p71/an1 p72/an2 p73/an3 p74/an4 p75/an5 p76/an6/da0 p77/an7/da1 av ss p40/tmci0 p41/tmo0 figure 1.4 pin arrangement (fp-80a, top view) rev. 3.0, 09/98, page 8 of 361 1.3.2 pin functions (1) pin assignments in each operating mode: table 1.2 lists the assignments of the pins of the fp-80a, cp-84, and cg-84 packages in each operating mode. table 1.2 pin assignments in each operating mode pin no. expanded modes single-chip mode cp-84 cg-84 fp-80a mode 1 mode 2 mode 3 prom mode 171d 6 d 6 p3 6 eo 6 2 ? v ss v ss v ss v ss 372d 7 d 7 p3 7 eo 7 473v ss v ss v ss v ss 574p8 0 p8 0 p8 0 nc 675p8 1 p8 1 p8 1 nc 776p8 2 p8 2 p8 2 nc 877p8 3 p8 3 p8 3 nc 978p8 4 / txd 1 / irq 3 p8 4 / txd 1 / irq 3 p8 4 / txd 1 / irq 3 nc 10 79 p8 5 / rxd 1 / irq 4 p8 5 / rxd 1 / irq 4 p8 5 / rxd 1 / irq 4 nc 11 80 p8 6 / sck 1 / irq 5 p8 6 / sck 1 / irq 5 p8 6 / sck 1 / irq 5 nc 12 1 res res res v pp 13 2 xtal xtal xtal nc 14 3 extal extal extal nc 15 4 md 1 md 1 md 1 v ss 16 5 md 0 md 0 md 0 v ss 17 6 nmi nmi nmi ea 9 18 7 stby stby stby v ss 19 8 v cc v cc v cc v cc 20 9 p5 2 / sck 0 p5 2 / sck 0 p5 2 / sck 0 nc 21 10 p5 1 / rxd 0 p5 1 / rxd 0 p5 1 / rxd 0 nc 22 11 p5 0 / txd 0 p5 0 / txd 0 p5 0 / txd 0 nc 23 12 v ss v ss v ss v ss 24 ? v ss v ss v ss v ss 25 13 wait wait p9 7 nc note: pins marked nc should be left unconnected. for details on p rom mode, refer to 14.2, prom mode. rev. 3.0, 09/98, page 9 of 361 table 1.2 pin assignments in each operating mode (cont) pin no. expanded modes single-chip mode cp-84 cg-84 fp-80a mode 1 mode 2 mode 3 prom mode 26 14 ff p9 6 / f nc 27 15 as as p9 5 nc 28 16 wr wr p9 4 nc 29 17 rd rd p9 3 nc 30 18 p9 2 / irq 0 p9 2 / irq 0 p9 2 / irq 0 pgm 31 19 p9 1 / irq 1 p9 1 / irq 1 p9 1 / irq 1 ea15 32 20 p9 0 / adtrg / irq 2 p9 0 / adtrg / irq 2 p9 0 / adtrg / irq 2 ea16 33 21 p6 0 / ftci p6 0 / ftci p6 0 / ftci nc 34 22 p6 1 / ftoa p6 1 / ftoa p6 1 / ftoa nc 35 23 p6 2 / ftia p6 2 / ftia p6 2 / ftia nc 36 24 p6 3 / ftib p6 3 / ftib p6 3 / ftib v cc 37 25 p6 4 / ftic p6 4 / ftic p6 4 / ftic v cc 38 26 p6 5 / ftid p6 5 / ftid p6 5 / ftid nc 39 27 p6 6 / ftob / irq 6 p6 6 / ftob / irq 6 p6 6 / ftob / irq 6 nc 40 28 p6 7 / irq 7 p6 7 / irq 7 p6 7 / irq 7 nc 41 ? v ss v ss v ss v ss 42 29 av cc av cc av cc v cc 43 30 p7 0 / an 0 p7 0 / an 0 p7 0 / an 0 nc 44 31 p7 1 / an 1 p7 1 / an 1 p7 1 / an 1 nc 45 32 p7 2 / an 2 p7 2 / an 2 p7 2 / an 2 nc 46 33 p7 3 / an 3 p7 3 / an 3 p7 3 / an 3 nc 47 34 p7 4 / an 4 p7 4 / an 4 p7 4 / an 4 nc 48 35 p7 5 / an 5 p7 5 / an 5 p7 5 / an 5 nc 49 36 p7 6 / an 6 /da 0 p7 6 / an 6 /da 0 p7 6 / an 6 /da 0 nc 50 37 p7 7 / an 7 /da 1 p7 7 / an 7 /da 1 p7 7 / an 7 /da 1 nc 51 38 av ss av ss av ss v ss 52 39 p4 0 / tmci 0 p4 0 / tmci 0 p4 0 / tmci 0 nc 53 40 p4 1 / tmo 0 p4 1 / tmo 0 p4 1 / tmo 0 nc 54 41 p4 2 / tmri 0 p4 2 / tmri 0 p4 2 / tmri 0 nc note: pins marked nc should be left unconnected. for details on prom mode, refer to 14.2, prom mode. rev. 3.0, 09/98, page 10 of 361 table 1.2 pin assignments in each operating mode (cont) pin no. expanded modes single-chip mode cp-84 cg-84 fp-80a mode 1 mode 2 mode 3 prom mode 55 42 p4 3 / tmci 1 p4 3 / tmci 1 p4 3 / tmci 1 nc 56 43 p4 4 / tmo 1 p4 4 / tmo 1 p4 4 / tmo 1 nc 57 44 p4 5 / tmri 1 p4 5 / tmri 1 p4 5 / tmri 1 nc 58 45 p4 6 / pw 0 p4 6 / pw 0 p4 6 / pw 0 nc 59 46 p4 7 / pw 1 p4 7 / pw 1 p4 7 / pw 1 nc 60 47 v cc v cc v cc v cc 61 48 a 15 p2 7 / a 15 p2 7 ce 62 49 a 14 p2 6 / a 14 p2 6 ea 14 63 50 a 13 p2 5 / a 13 p2 5 ea 13 64 ? v ss v ss v ss v ss 65 51 a 12 p2 4 / a 12 p2 4 ea 12 66 52 a 11 p2 3 / a 11 p2 3 ea 11 67 53 a 10 p2 2 / a 10 p2 2 ea 10 68 54 a 9 p2 1 / a 9 p2 1 oe 69 55 a 8 p2 0 / a 8 p2 0 ea 8 70 56 v ss v ss v ss v ss 71 57 a 7 p1 7 / a 7 p1 7 ea 7 72 58 a 6 p1 6 / a 6 p1 6 ea 6 73 59 a 5 p1 5 / a 5 p1 5 ea 5 74 60 a 4 p1 4 / a 4 p1 4 ea 4 75 61 a 3 p1 3 / a 3 p1 3 ea 3 76 62 a 2 p1 2 / a 2 p1 2 ea 2 77 63 a 1 p1 1 / a 1 p1 1 ea 1 78 64 a 0 p1 0 / a 0 p1 0 ea 0 79 65 d 0 d 0 p3 0 eo 0 80 66 d 1 d 1 p3 1 eo 1 81 67 d 2 d 2 p3 2 eo 2 82 68 d 3 d 3 p3 3 eo 3 83 69 d 4 d 4 p3 4 eo 4 84 70 d 5 d 5 p3 5 eo 5 note: pins marked nc should be left unconnected. for details on prom mode, refer t o 14.2, prom mode. rev. 3.0, 09/98, page 11 of 361 (2) pin functions: table 1.3 gives a concise description of the function of each pin. table 1.3 pin functions pin no. type symbol cg-84 cp-84 fp-80a i/o name and function power v cc 19, 60 8, 47 i power: connected to the power supply (+5v). connect both vcc pins to the system power supply (+5v). v ss 2, 4, 23, 24, 41, 64, 70 12, 56, 73 i ground: connected to ground (0v). connect all vss pins to the system power s upply (0v). clock xtal 13 2 i crystal: connected to a crystal oscillator. the crystal frequency should be double the desired system clock frequency extal 14 3 i external crystal: connected to a crystal oscillator or external clock. the frequency of the external clock should be double the desired system clock frequency. see section 15.2, oscillator circuit, for examples of connections to a crystal and external clock. ? 26 14 o system clock: supplies the system clock to peripheral devices. res 12 1 i reset: a low input causes the chip to reset. system control stby 18 7 i standby: a transition to the hardware standby mode (a power-down state) occurs when a low input is received at the stby pin. address bus a 15 to a 0 61 to 63, 65 to 69, 71 to 78 48 to 55, 57 to 64 o address bus: address output pins. data bus d 7 to d 0 3, 1, 84 to 79 72 to 65 i/o data bus: 8-bit bidirectional data bus. rev. 3.0, 09/98, page 12 of 361 table 1.3 pin functions (cont) pin no. type symbol cg-84 cp-84 fp-80a i/o name and function bus control wait 25 13 i wait: requests the cpu to insert tw states into the bus cycle w hen an external address is accessed. rd 29 17 o read: goes low to indicate that the cpu is reading an external address. wr 28 16 o write: goes low to indicate that the cpu is writing to an external address. as 27 15 o address strobe: goes low to indicate that there is a valid address on the address bus. interrupt signals nmi 17 6 i nonmaskable interrupt: highest-priority interrupt request. the nmieg bit in the system control register determines whether the interrupt is requested on the rising or falling edge of the nmi input. irq 0 to irq 7 30 to 32, 9 to 11, 39, 40 18 to 20, 78 to 80, 27, 28 i interrupt request 0 to 7: maskable interrupt request pins. md 1 , md 0 15 16 4 5 i mode: input pins for setting the mcu operating mode according to the table below. operating mode control md 1 md 0 mode description 0 0 mode 0 setting prohibited 0 1 mode 1 expanded mode with on-chip rom disabled 1 0 mode 2 expanded mode with on-chip rom enabled 1 1 mode 3 single-chip mode these pins must not be changed during mcu operation. txd 0 , txd 1 22 9 11 78 o transmit data (channels 0 and 1): data output pins for the serial communication interface. rxd 0 , rxd 1 21 10 10 79 i receive data (channels 0 and 1): data input pins for the serial communication interface. serial communi- cation interface sck 0 , sck 1 20 11 9 80 i/o serial clock (channels 0 and 1): input/output pins for the serial clock. rev. 3.0, 09/98, page 13 of 361 table 1.3 pin functions (cont) pin no. type symbol cg-84 cp-84 fp-80a i/o name and function ftoa, ftob 34 39 22 27 o frt output compare a and b: output pins controlled by comparators a and b of the free- running timer. 16-bit free- running timer ftci 33 21 i frt counter clock input: input pin for an external clock signal for the free-running timer. ftia to ftid 35 to 38 23 to 26 i frt input capture a to d: input capture pins for the free-running timer. 8-bit timer tmo 0 , tmo 1 53 56 40 43 o 8-bit timer output (channels 0 and 1): compare-match output pins for the 8-bit timers. tmci 0 , tmci 1 52 55 39 42 i 8-bit timer counter clock input (channels 0 and 1): external clock input pins for the 8-bit timer counters. tmri 0 , tmri 1 54 57 41 44 i 8-bit timer counter reset input (channels 0 and 1): a high input at these pins resets the 8- bit timer counters. pwm timer pw 0 , pw 1 58 59 45 46 o pwm timer output (channels 0 and 1): pulse-width modulation timer output pins. an 7 to an 0 50 to 43 37 to 30 i analog input: analog signal input pins for the a/d converter. a/d converter adtrg 32 20 i a/d trigger: external trigger input for starting the a/d converter. d/a converter da 0 da 1 49 50 36 37 o analog output: analog signal output pins for the d/a converter. av cc 42 29 i analog reference voltage: reference voltage pin for the a/d and d/a converters. if the a/d and d/a converters are not used, connect avcc to the system power s upply (+5v). a/d and d/a converters av ss 51 38 i analog ground: ground pin for the a/d and d/a converters.connect to system gr ound (0v). rev. 3.0, 09/98, page 14 of 361 table 1.3 pin functions (cont) pin no. type symbol cg-84 cp-84 fp-80a i/o name and function general- purpose i/o p1 7 to p1 0 71 to 78 57 to 64 i/o port 1: an 8-bit input/output port with programmable mos input pull-ups and led driving capability. the direction of each bit can be selected in the port 1 data direction register (p1ddr). p2 7 to p2 0 61 to 63, 65 to 69 48 to 55 i/o port 2: an 8-bit input/output port with programmable mos input pull-ups and led driving capability. the direction of each bit can be selected in the port 2 data direction register (p2ddr). p3 7 to p3 0 3, 1, 84 to 79 72 to 65 i/o port 3: an 8-bit input/output port with programmable mos input pull-ups. the direction of each bit can be selected in the port 3 data direction register (p3ddr). p4 7 to p4 0 59 to 52 46 to 39 i/o port 4: an 8-bit input/output port. the direction of each bit can be selected in the port 4 data direction register (p4ddr). p5 2 to p5 0 20 to 22 9 to 11 i/o port 5: a 3-bit input/output port. the direction of each bit can be selected in the port 5 data direction register (p5ddr). p6 7 to p6 0 40 to 33 28 to 21 i/o port 6: an 8-bit input/output port. the direction of each bit can be selected in the port 6 data direction register (p6ddr). p7 7 to p7 0 50 to 43 37 to 30 i port 7: an 8-bit input port. p8 6 to p8 0 11 to 5 80 to 74 i/o port 8: a 7-bit input/output port. the direction of each bit can be selected in the port 8 data direction register (p8ddr). p9 7 to p9 0 25 to 32 13 to 20 i/o port 9: an 8-bit input/output port. the direction of each bit (except for p96) can be selected in the port 9 data direction register (p9ddr). rev. 3.0, 09/98, page 15 of 361 section 2 cpu 2.1 overview the h8/338 series has the h8/300 cpu: a fast central processing unit with eight 16-bit general registers (also configurable as 16 eight-bit registers) and a concise instruction set designed for high-speed operation. 2.1.1 features the main features of the h8/300 cpu are listed below. two-way register configuration ? sixteen 8-bit general registers, or ? eight 16-bit general registers instruction set with 57 basic instructions, including: ? multiply and divide instructions ? powerful bit-manipulation instructions eight addressing modes ? register direct (rn) ? register indirect (@rn) ? register indirect with displacement (@(d:16, rn)) ? register indirect with post-increment or pre-decrement (@rn+ or @ - rn) ? absolute address (@aa:8 or @aa:16) ? immediate (#xx:8 or #xx:16) ? pc-relative (@(d:8, pc)) ? memory indirect (@@aa:8) maximum 64k-byte address space high-speed operation ? all frequently-used instructions are executed in two to four states ? the maximum clock rate is 10mhz ? 8- or 16-bit register-register add or subtract: 0.2s ? 8 8-bit multiply: 1.4s ? 16 ? 8-bit divide: 1.4s power-down mode ? sleep instruction rev. 3.0, 09/98, page 16 of 361 2.2 register configuration figure 2.1 shows the register structure of the cpu. there are two groups of registers: the general registers and control registers. sp: stack pointer pc: program counter ccr: condition code register carry flag overflow flag zero flag negative flag half-carry flag interrupt mask bit user bit user bit 07 0 7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l 0 15 pc ccr (sp) 7 i 6 u 5 h 4 u 3 n 2 z 1 v 0 c figure 2.1 cpu registers rev. 3.0, 09/98, page 17 of 361 2.2.1 general registers all the general registers can be used as both data registers and address registers. when used as address registers, the general registers are accessed as 16-bit registers (r0 to r7). when used as data registers, they can be accessed as 16-bit registers, or the high and low bytes can be accessed separately as 8-bit registers (r0h to r7h and r0l to r7l). r7 also functions as the stack pointer, used implicitly by hardware in processing interrupts and subroutine calls. in assembly-language coding, r7 can also be denoted by the letters sp. as indicated in figure 2.2, r7 (sp) points to the top of the stack. sp (r7) unused area stack area figure 2.2 stack pointer 2.2.2 control registers the cpu control registers include a 16-bit program counter (pc) and an 8-bit condition code register (ccr). (1) program counter (pc): this 16-bit register indicates the address of the next instruction the cpu will execute. each instruction is accessed in 16 bits (1 word), so the least significant bit of the pc is ignored (always regarded as 0). (2) condition code register (ccr): this 8-bit register contains internal status information, including carry (c), overflow (v), zero (z), negative (n), and half-carry (h) flags and the interrupt mask bit (i). bit 7 ? interrupt mask bit (i): when this bit is set to 1, all interrupts except nmi are masked. this bit is set to 1 automatically by a reset and at the start of interrupt handling. bit 6 ? user bit (u): this bit can be written and read by software (using the ldc, stc, andc, orc, and xorc instructions). bit 5 ? half-carry flag (h): this flag is set to 1 when the add.b, addx.b, sub.b, subx.b, neg.b, or cmp.b instruction causes a carry or borrow out of bit 3, and is cleared to rev. 3.0, 09/98, page 18 of 361 0 otherwise. similarly, it is set to 1 when the add.w, sub.w, or cmp.w instruction causes a carry or borrow out of bit 11, and cleared to 0 otherwise. it is used implicitly in the daa and das instructions. bit 4 ? user bit (u): this bit can be written and read by software (using the ldc, stc, andc, orc, and xorc instructions). bit 3 ? negative flag (n): this flag indicates the most significant bit (sign bit) of the result of an instruction. bit 2 ? zero flag (z): this flag is set to 1 to indicate a zero result and cleared to 0 to indicate a nonzero result. bit 1 ? overflow flag (v): this flag is set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. bit 0 ? carry flag (c): this flag is used by: add and subtract instructions, to indicate a carry or borrow at the most significant bit of the result shift and rotate instructions, to store the value shifted out of the most significant or least significant bit bit manipulation and bit load instructions, as a bit accumulator the ldc, stc, andc, orc, and xorc instructions enable the cpu to load and store the ccr, and to set or clear selected bits by logic operations. the n, z, v, and c flags are used in conditional branching instructions (b cc ). for the action of each instruction on the flag bits, see the h8/300 series programming manual . 2.2.3 initial register values when the cpu is reset, the program counter (pc) is loaded from the vector table and the interrupt mask bit (i) in the ccr is set to 1. the other ccr bits and the general registers are not initialized. in particular, the stack pointer (r7) is not initialized. to prevent program crashes the stack pointer should be initialized by software, by the first instruction executed after a reset. rev. 3.0, 09/98, page 19 of 361 2.3 addressing modes 2.3.1 addressing mode the h8/300 cpu supports eight addressing modes. each instruction uses a subset of these addressing modes. table 2.1 addressing modes no. addressing mode symbol (1) register direct rn (2) register indirect @rn (3) register indirect with displacement @(d:16, rn) (4) register indirect with post-increment register indirect with pre-decrement @rn+ @ - rn (5) absolute address @aa:8 or @aa:16 (6) immediate #xx:8 or #xx:16 (7) program-counter-relative @(d:8, pc) (8) memory indirect @@aa:8 (1) register direct ? rn: the register field of the instruction specifies an 8- or 16-bit general register containing the operand. in most cases the general register is accessed as an 8-bit register. only the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits ? 8 bits) instructions have 16-bit operands. (2) register indirect ? @rn: the register field of the instruction specifies a 16-bit general register containing the address of the operand. (3) register indirect with displacement ? @(d:16, rn): this mode, which is used only in mov instructions, is similar to register indirect but the instruction has a second word (bytes 3 and 4) which is added to the contents of the specified general register to obtain the operand address. for the mov.w instruction, the resulting address must be even. (4) register indirect with post-increment or pre-decrement ? @rn+ or @ - rn: register indirect with post-increment ? @rn+ the @rn+ mode is used with mov instructions that load registers from memory. it is similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction is incremented after the operand is accessed. the size of the increment is 1 or 2 depending on the size of the operand: 1 for mov.b; 2 for mov.w. for mov.w, the original contents of the 16-bit general register must be even. rev. 3.0, 09/98, page 20 of 361 register indirect with pre-decrement ? @ - rn the @ - rn mode is used with mov instructions that store register contents to memory. it is similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction is decremented before the operand is accessed. the size of the decrement is 1 or 2 depending on the size of the operand: 1 for mov.b; 2 for mov.w. for mov.w, the original contents of the 16-bit general register must be even. (5) absolute address ? @aa:8 or @aa:16: the instruction specifies the absolute address of the operand in memory. the mov.b instruction uses an 8-bit absolute address of the form h'ffxx. the upper 8 bits are assumed to be 1, so the possible address range is h'ff00 to h'ffff (65280 to 65535). the mov.b, mov.w, jmp, and jsr instructions can use 16-bit absolute addresses. (6) immediate ? #xx:8 or #xx:16: the instruction contains an 8-bit operand in its second byte, or a 16-bit operand in its third and fourth bytes. only mov.w instructions can contain 16-bit immediate values. the adds and subs instructions implicitly contain the value 1 or 2 as immediate data. some bit manipulation instructions contain 3-bit immediate data (#xx:3) in the second or fourth byte of the instruction, specifying a bit number. (7) program-counter-relative ? @(d:8, pc): this mode is used to generate branch addresses in the b cc and bsr instructions. an 8-bit value in byte 2 of the instruction code is added as a sign-extended value to the program counter contents. the result must be an even number. the possible branching range is - 126 to +128 bytes ( - 63 to +64 words) from the current address. (8) memory indirect ? @@aa:8: this mode can be used by the jmp and jsr instructions. the second byte of the instruction code specifies an 8-bit absolute address from h'0000 to h'00ff (0 to 255). the word located at this address contains the branch address. the upper 8 bits of the absolute address are an 0 (h'00), thus the branch address is limited to values from 0 to 255 (h'0000 to h'00ff). note that addresses h'0000 to h'0047 (0 to 71) are located in the vector table. if an odd address is specified as a branch destination or as the operand address of a mov.w instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. see section 2.4.2, memory data formats, for further information. rev. 3.0, 09/98, page 21 of 361 2.3.2 how to calculate where the execution starts table 2.2 shows how to calculate the effective address (ea: effective address) for each addressing mode. in the operation instruction, 1) register direct, as well as 6) immediate (for each instruction, add.b, addx, subx, cmp.b, and, or, xor) are used. in the move instruction, 7) program counter relative and 8) all addressing mode to delete the memory indirect can be used. in the bit manipulation instruction for the operand specifications, 1) register direct, 2) register indirect, as well as 5) absolute address (8 bit) can be used. furthermore, to specify the bit number within the operand, 1) register direct (for each instruction, bset, bclr, bnot, btst) as well as 6) immediate (3 bit) can be used independently. rev. 3.0, 09/98, page 22 of 361 table 2.2 effective address calculation addressing mode and instruction format op reg 76 3 40 15 no. effective address calculation effective address 1 register direct, rn operands are contained in registers regm and regn register indirect, @rn 16-bit register contents 0 15 register indirect with displacement, @(d:16, rn) op regm regn 87 3 40 15 op reg 76 3 40 15 disp op reg 76 3 40 15 register indirect with post-increment, @rn+ op reg 76 3 40 15 register indirect with pre-decrement, @?n 2 3 4 1 for a byte operand, 2 for a word operand 0 15 disp 0 15 0 15 0 15 1 or 2 0 15 0 15 1 or 2 0 15 regm 30 regn 30 16-bit register contents 16-bit register contents 16-bit register contents * * * note: rev. 3.0, 09/98, page 23 of 361 table 2.2 effective address calculation (cont) addressing mode and instruction format no. effective address calculation effective address 5 absolute address @aa:8 operand is 1- or 2-byte immediate data @aa:16 op 87 0 15 op 0 15 imm op disp 70 15 pc-relative @(d:8, pc) 6 7 0 15 pc contents 0 15 0 15 abs h'ff 87 0 15 0 15 abs op #xx:16 op 87 0 15 imm immediate #xx:8 8 sign extension disp rev. 3.0, 09/98, page 24 of 361 table 2.2 effective address calculation (cont) table 3-2. effective address calculation (3) addressing mode and instruction format no. effective address calculation effective address 8 memory indirect, @@aa:8 op 87 0 15 memory contents (16 bits) 0 15 abs h'00 87 0 15 notation reg: op: disp: imm: abs: general register operation code displacement immediate data absolute address rev. 3.0, 09/98, page 25 of 361 2.4 data formats the h8/300 cpu can process 1-bit data, 4-bit (bcd) data, 8-bit (byte) data, and 16-bit (word) data. bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a byte operand. all arithmetic and logic instructions except adds and subs can operate on byte data. the daa and das instruction perform decimal arithmetic adjustments on byte data in packed bcd form. each nibble of the byte is treated as a decimal digit. the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits ? 8 bits) instructions operate on word data. rev. 3.0, 09/98, page 26 of 361 2.4.1 data formats in general registers data of all the sizes above can be stored in general registers as shown in figure 2.3. 7 rnh 1-bit data data type register no. data format 6543210 70 don't care 7 rnl 1-bit data 6543210 70 don't care msb rnh byte data lsb 70 don't care msb rnl byte data lsb 70 don't care msb rn word data lsb 15 0 upper digit rnh 4-bit bcd data lower digit 743 0 743 0 don't care rnl 4-bit bcd data upper digit lower digit don't care rnh rnl msb lsb legend upper digit of general register lower digit of general register most significant bit least significant bit it figure 2.3 register data formats rev. 3.0, 09/98, page 27 of 361 2.4.2 memory data formats figure 2.4 indicates the data formats in memory. word data stored in memory must always begin at an even address. in word access the least significant bit of the address is regarded as 0. if an odd address is specified, no address error occurs but the access is performed at the preceding even address. this rule affects mov.w instructions and branching instructions, and implies that only even addresses should be stored in the vector table. 7 msb msb msb msb msb address n address n even address odd address even address odd address even address odd address 654 upper 8 bits lower 8 bits ccr ccr * 3210 lsb lsb lsb lsb lsb 70 data format address 1-bit data byte data word data byte data (ccr) on stack word data on stack data type note: * ignored when returned legend ccr: condition code register figure 2.4 memory data formats when the stack is addressed by register r7, it must always be accessed a word at a time. when the ccr is pushed on the stack, two identical copies of the ccr are pushed to make a complete word. when they are returned, the lower byte is ignored. rev. 3.0, 09/98, page 28 of 361 2.5 instruction set table 2.3 lists the h8/300 instruction set. table 2.3 instruction classification function instructions types data transfer mov, movtpe* 3 , movfpe* 3 , push* 1 , pop* 1 3 arithmetic operations add, sub, addx, subx, inc, dec, adds, subs, daa, das, mulxu, divxu, cmp, neg 14 logic operations and, or, xor, not 4 shift shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr 8 bit manipulation bset, bclr, bnot, btst, band, biand, bor, bior, bxor, bixor, bld, bild, bst, bist 14 branch bcc* 2 , jmp, bsr, jsr, rts 5 system control rte, sleep, ldc, stc, andc, orc, xorc, nop 8 block data transfer eepmov 1 total 57 notes: 1. push rn is equivalent to mov.w rn, @ - sp. pop rn is equivalent to mov.w @sp+, rn. 2. b cc is a conditional branch instruction in which cc represents a condition code. 3. not supported by the h8/338 series. the following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. the notation used is defined next. rev. 3.0, 09/98, page 29 of 361 operation notation rd general register (destination) rs general register (source) rn general register (ead) destination operand (eas) source operand sp stack pointer pc program counter ccr condition code register n n (negative) flag of ccr z z (zero) flag of ccr v v (overflow) flag of ccr c c (carry) flag of ccr #imm immediate data #xx:3 3-bit immediate data #xx:8 8-bit immediate data #xx:16 16-bit immediate data disp displacement + addition - subtraction multiplication ? division and logical or logical ? exclusive or logical ? move ? not rev. 3.0, 09/98, page 30 of 361 2.5.1 data transfer instructions table 2.4 describes the data transfer instructions. figure 2.5 shows their object code formats. table 2.4 data transfer instructions instruction size * function mov b/w (eas) ? rd, rs ? (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. the rn, @rn, @(d:16, rn), @aa:16, #xx:8 or #xx:16, @ - rn, and @rn+ addressing modes are available for byte or word data. the @aa:8 addressing mode is available for byte data only. the @ - r7 and @r7+ modes require word operands. do not specify byte size for these two modes. movtpe b not supported by the h8/338 series. movfpe b not supported by the h8/338 series. push wrn ? @ - sp pushes a 16-bit general register onto the stack. equivalent to mov.w rn, @ - sp. pop w @sp+ ? rn pops a 16-bit general register from the stack. equivalent to mov.w @sp+, rn. note: size: operand size b: byte w: word rev. 3.0, 09/98, page 31 of 361 rm rn 0mov 7 8 15 op r m r n rn @rm, or @rm rn op r n r m @(d:16, rm) rn,or rn @(d:16, rm) op r n r m disp. @rm+ rn, or rn @-rm op r n r m @aa:8 rn, or rn @aa:8 op r n abs. @aa:16 rn. or rn @aa:16 op r n abs. # xx :8 rn op r n #imm. # xx :16 rn op r n #imm. movfre, movtpe op r n abs. push, pop op r n op r m , r n disp. abs. imm legend : operation field : register field : displacement : absolute address : immediate data figure 2.5 data transfer instruction codes rev. 3.0, 09/98, page 32 of 361 2.5.2 arithmetic operations table 2.5 describes the arithmetic instructions. see figure 2.6 in section 2.5.4, shift operations for their object codes. table 2.5 arithmetic instructions instruction size * function add sub b/w rd rs ? rd, rd + #imm ? rd performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. immediate data cannot be subtracted from data in a general register. word data can be added or subtracted only when both words are in general registers. addx subx b rd rs c ? rd, rd #imm c ? rd performs addition or subtraction with carry or borrow on byte data in two general registers, or addition or subtraction on immediate data and data in a general register. inc dec b rd #1 ? rd increments or decrements a general register. adds subs w rd #imm ? rd adds or subtracts immediate data to or from data in a general register. the immediate data must be 1 or 2. daa das b rd decimal adjust ? rd decimal-adjusts (adjusts to packed bcd) an addition or subtraction result in a general register by referring to the ccr. mulxu brd rs ? rd performs 8-bit 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result. divxu brd ? rs ? rd performs 16-bit ? 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder. cmp b/w rd - rs, rd - #imm compares data in a general register with data in another general register or with immediate data. word data can be compared only between two general registers. neg b0 - rd ? rd obtains the two?s complement (arithmetic complement) of data in a general register. note: size: operand size b: byte w: word rev. 3.0, 09/98, page 33 of 361 2.5.3 logic operations table 2.6 describes the four instructions that perform logic operations. see figure 2.6 in section 2.5.4, shift operations, for their object codes. table 2.6 logic operation instructions instruction size * function and brd rs ? rd, rd #imm ? rd performs a logical and operation on a general register and another general register or immediate data. or brd rs ? rd, rd #imm ? rd performs a logical or operation on a general register and another general register or immediate data. xor brd ? rs ? rd, rd ? #imm ? rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b ? (rd) ? (rd) obtains the one?s complement (logical complement) of general register contents. note: size: operand size b: byte 2.5.4 shift operations table 2.7 describes the eight shift instructions. figure 2.6 shows the object code formats of the arithmetic, logic, and shift instructions. table 2.7 shift instructions instruction size * function shal shar b rd shift ? rd performs an arithmetic shift operation on general register contents. shll shlr b rd shift ? rd performs a logical shift operation on general register contents. rotl rotr b rd rotate ? rd rotates general register contents. rotxl rotxr b rd rotate through carry ? rd rotates general register contents through the c (carry) bit. note: size: operand size b: byte rev. 3.0, 09/98, page 34 of 361 add, aub, cmp addx, subx(r m ), mulxu, divxu 0 7 8 15 op r m r n adds, subs, inc, dec, daa, das, neg, not op r n add, addx, subx, cmp (# xx :8) op r n #imm. and, or, xor(r m ) op r m r n and, or, xor(# xx :8) op r n #imm. shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr op r n op r m , r n imm legend: : operation field : register field : immediate data figure 2.6 arithmetic, logic, and shift instruction codes rev. 3.0, 09/98, page 35 of 361 2.5.5 bit manipulations table 2.8 describes the bit-manipulation instructions. figure 2.7 shows their object code formats. table 2.8 bit-manipulation instructions instruction size * function bset b1 ? ( rev. 3.0, 09/98, page 36 of 361 table 2.8 bit-manipulation instructions (cont) instruction size * function bixor bc ? ? [( rev. 3.0, 09/98, page 37 of 361 before execution of bclr instruction p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 input/output input input output output output output output output pin state low high low low low low low low ddr 00111111 dr 10000000 execution of bclr instruction bclr #0, @p4ddr ; clear bit 0 in data direction register after execution of bclr instruction p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 input/output output output output output output output output input pin state low high low low low low low high ddr 11111110 dr 10000000 explanation: to execute the bclr instruction, the cpu begins by reading p4ddr. since p4ddr is a write-only register, it is read as h'ff, even though its true value is h'3f. next the cpu clears bit 0 of the read data, changing the value to h'fe. finally, the cpu writes this value (h'fe) back to p4ddr to complete the bclr instruction. as a result, p4 0 ddr is cleared to 0, making p4 0 an input pin. in addition, p4 7 ddr and p4 6 ddr are set to 1, making p4 7 and p4 6 output pins. rev. 3.0, 09/98, page 38 of 361 operand: register direct (rn) bit no.: immediate (#xx:3) 0 bset, bclr, bnot, btst 7 8 15 op #imm. r n operand: register direct (rn) bit no.: register direct (rm) op r m r n operand: register indirect (@rn) op r n 0 0 0 0 bit no.: immediate (#xx:3) op #imm. 0 0 0 0 operand: register indirect (@rn) op r n 0 bit no.: register direct (rm) op r m 0 operand: absolute (@aa:8) op abs. bit no.: immediate (#xx:3) op #imm. 0 operand: absolute (@aa:8) op abs. bit no.: register direct (rm) band, bor, bxor, bld, bst op r m 0 operand: register direct (rn) bit no.: immediate (#xx:3) op #imm. r n operand: register indirect (@rn) op r n 0 bit no.: immediate (#xx:3) op #imm. 0 operand: absolute (@aa:8) op abs. bit no.: immediate (#xx:3) biand, bior, bixor, bild, bist op #imm. 0 operand: register indirect (@rn) op r n 0 bit no.: immediate (#xx:3) op #imm. 0 operand: absolute (@aa:8) op abs. bit no.: immediate (#xx:3) op 0 operand: register direct (rn) bit no.: immediate (#xx:3) op r n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 #imm. #imm. op r m , r n abs. imm legend: : operation field : register field : absolute address : immediate data figure 2.7 bit manipulation instruction codes rev. 3.0, 09/98, page 39 of 361 2.5.6 branching instructions table 2.9 describes the branching instructions. figure 2.8 shows their object code formats. table 2.9 branching instructions instruction size function b cc ? branches if condition cc is true. mnemonic cc field description condition bra (bt) 0 0 0 0 always (true) always brn (bf) 0 0 0 1 never (false) never bhi 0 0 1 0 high c z = 0 bls 0 0 1 1 low or same c z = 1 bcc (bhs) 0 1 0 0 carry clear c = 0 (high or same) bcs (blo) 0 1 0 1 carry set (low) c = 1 bne 0 1 1 0 not equal z = 0 beq 0 1 1 1 equal z = 1 bvc 1 0 0 0 overflow clear v = 0 bvs 1 0 0 1 overflow set v = 1 bpl 1 0 1 0 plus n = 0 bmi 1 0 1 1 minus n = 1 bge 1 1 0 0 greater or equal n ? v = 0 blt 1 1 0 1 less than n ? v = 1 bgt 1 1 1 0 greater than z (n ? v) = 0 ble 1 1 1 1 less or equal z (n ? v) = 1 jmp ? branches unconditionally to a specified address. jsr ? branches to a subroutine at a specified address. bsr ? branches to a subroutine at a specified displacement from the current address. rts ? returns from a subroutine rev. 3.0, 09/98, page 40 of 361 b cc 0 7 8 15 op cc disp. jmp(@rm) op r m 0000 jsr(@rm) op r m 0000 jmp(@@aa:8) op abs. jsr(@@aa:8) op abs. rts op bsr op disp. jmp(@aa:16) op abs. jsr(@aa:16) op abs. op cc r m disp. abs. legend: : operation field : condition field : register field : displacement : absolute address figure 2.8 branching instruction codes rev. 3.0, 09/98, page 41 of 361 2.5.7 system control instructions table 2.10 describes the system control instructions. figure 2.9 shows their object code formats. table 2.10 system control instructions instruction size function rte ? returns from an exception-handling routine. sleep ? causes a transition to the power-down state. ldc b rs ? ccr, #imm ? ccr moves immediate data or general register contents to the condition code register. stc b ccr ? rd copies the condition code register to a specified general register. andc b ccr #imm ? ccr logically ands the condition code register with immediate data. orc b ccr #imm ? ccr logically ors the condition code register with immediate data. xorc b ccr ? #imm ? ccr logically exclusive-ors the condition code register with immediate data. nop ? pc + 2 ? pc only increments the program counter. note: size: operand size b: byte rev. 3.0, 09/98, page 42 of 361 rte, sleep, nop 0 7 8 15 op ldc, stc(r n ) op r n andc, orc, xorc, ldc (# xx :8) op #imm. op r n #imm. : operation field : register field : immediate data legend: figure 2.9 system control instruction codes 2.5.8 block data transfer instruction table 2.11 describes the eepmov instruction. figure 2.10 shows its object code format. table 2.11 block data transfer instruction/eeprom write operation instruction size function eepmov ? if r4l 1 0 then repeat @r5+ ? @r6+ r4l - 1 ? r4l until r4l = 0 else next; moves a data block according to parameters set in general registers r4l, r5, and r6. r4l: size of block (bytes) r5: starting source address r6: starting destination address execution of the next instruction starts as soon as the block transfer is completed. rev. 3.0, 09/98, page 43 of 361 op 87 15 0 eeprom op: operation field op figure 2.10 block data transfer instruction/eeprom write operation code notes on eepmov instruction note 1 1. the eepmov instruction is a block data transfer instruction. it moves the number of bytes specified by r4l from the address specified by r5 to the address specified by r6. r5 ? r5 + r4l ? ? r6 ? r6 + r4l 2. when setting r4l and r6, make sure that the final destination address (r6 + r4l) does not exceed h'ffff. the value in r6 must not change from h'ffff to h'0000 during execution of the instruction. h'ffff not allowed r5 ? r5 + r4l ? ? r6 ? r6 + r4l note 2 cpu will malfunction after eepmov instruction execution, in the following conditions. eepmov instruction performs block data transfer function. condition when the following conditions are all true: ? the lsi is set to expanded mode (i.e. mode 1 or mode 2). ? the destination address of eepmov instruction is external area. ? at least one wait state is inserted to the last write bus cycle to the destination address by eepmov instruction. rev. 3.0, 09/98, page 44 of 361 2.6 cpu states the cpu has three states: the program execution state, exception-handling state, and power-down state. the power-down state is further divided into three modes: the sleep mode, software standby mode, and hardware standby mode. figure 2.11 summarizes these states, and figure 2.12 shows a map of the state transitions. the cpu executes successive program instructions. a transient state triggered by a reset or interrupt. the cpu executes a hardware sequence that includes loading the program counter from the vector table. a state in which some or all of the chip functions are stopped to conserve power. state program execution state exception-handling state power-down state sleep mode software standby mode hardware standby mode figure 2.11 operating states rev. 3.0, 09/98, page 45 of 361 program execution state exception- handling state interrupt request nmi or irq0 to irq2 sleep instruction with ssby bit set sleep instruction power-down state res= 1 stby= 1, res= 0 exception handing exception handing request reset state sleep mode software standby mode hardware standby mode notes: 1. 2. a transition to the reset state occurs when res goes low, except when the chip is in the hardware standby mode. a transition from any state to the hardware standby mode occurs when stby goes low. figure 2.12 state transitions 2.6.1 program execution state in this state the cpu executes program instructions. 2.6.2 exception-handling state the exception-handling state is a transient state that occurs when the cpu is reset or accepts an interrupt. in this state the cpu carries out a hardware-controlled sequence that prepares it to execute a user-coded exception-handling routine. in the hardware exception-handling sequence the cpu does the following: (1) saves the program counter and condition code register to the stack (except in the case of a reset). (2) sets the interrupt mask (i) bit in the condition code register to 1. (3) fetches the start address of the exception-handling routine from the vector table. (4) branches to that address, returning to the program execution state. see section 4, exception handling, for further information on the exception-handling state. rev. 3.0, 09/98, page 46 of 361 2.6.3 power-down state the power-down state includes three modes: the sleep mode, the software standby mode, and the hardware standby mode. (1) sleep mode: the sleep mode is entered when a sleep instruction is executed. the cpu halts, but cpu register contents remain unchanged and the on-chip supporting modules continue to function. (2) software standby mode: the software standby mode is entered if the sleep instruction is executed while the ssby (software standby) bit in the system control register (syscr) is set. the cpu and all on-chip supporting modules halt. the on-chip supporting modules are initialized, but the contents of the on-chip ram and cpu registers remain unchanged. i/o port outputs also remain unchanged. (3) hardware standby mode: the hardware standby mode is entered when the input at the stby pin goes low. all chip functions halt, including i/o port output. the on-chip supporting modules are initialized, but on-chip ram contents are held. see section 14, power-down state, for further information. rev. 3.0, 09/98, page 47 of 361 2.7 access timing and bus cycle the cpu is driven by the system clock ( f ). the period from one rising edge of the system clock to the next is referred to as a state. memory access is performed in a two- or three-state bus cycle. on-chip memory, on-chip supporting modules, and external devices are accessed in different bus cycles as described below. 2.7.1 access to on-chip memory (ram and rom) on-chip rom and ram are accessed in a cycle of two states designated t 1 and t 2 . either byte or word data can be accessed, via a 16-bit data bus. figure 2.13 shows the on-chip memory access cycle. figure 2.14 shows the associated pin states. ? internal address bus internal read signal internal data bus (read) internal data bus (write) internal write signal bus cycle t1 state t2 state read data write data address figure 2.13 on-chip memory access cycle rev. 3.0, 09/98, page 48 of 361 ? address bus rd: high data bus: high impedance state as: high wr: high bus cycle t1 state t2 state address figure 2.14 pin states during on-chip memory access cycle rev. 3.0, 09/98, page 49 of 361 2.7.2 access to on-chip register field and external devices the on-chip register field (i/o ports, dual-port ram, on-chip supporting module registers, etc.) and external devices are accessed in a cycle consisting of three states: t 1 , t 2 , and t 3 . only one byte of data can be accessed per cycle, via an 8-bit data bus. access to word data or instruction codes requires two consecutive cycles (six states). figure 2.15 shows the access cycle for the on-chip register field. figure 2.16 shows the associated pin states. figures 2.17 (a) and (b) show the read and write access timing for external devices. ? internal address bus internal read signal internal data bus (read) internal write signal internal data bus (write) bus cycle t1 state t2 state address t3 state read data write data figure 2.15 on-chip register field access cycle rev. 3.0, 09/98, page 50 of 361 ? address bus as: high rd: high wr: high data bus: high impedance state bus cycle t1 state t2 state address t3 state figure 2.16 pin states during on-chip register field access cycle rev. 3.0, 09/98, page 51 of 361 address bus as rd wr: high data bus read cycle t1 state t2 state address t3 state read data ? figure 2.17 (a) external device access timing (read) rev. 3.0, 09/98, page 52 of 361 address bus as wr rd: high data bus write cycle t1 state t2 state write data address t3 state ? figure 2.17 (b) external device access timing (write) rev. 3.0, 09/98, page 53 of 361 section 3 mcu operating modes and address space 3.1 overview 3.1.1 mode selection the h8/338 series operates in three modes numbered 1, 2, and 3. the mode is selected by the inputs at the mode pins (md 1 and md 0 ) when the chip comes out of a reset. see table 3.1. the romless versions of the h8/338 series (hd6413388, hd6413378) can be used only in mode 1 (expanded mode with on-chip rom disabled). table 3.1 operating modes mode md1 md0 address space on-chip rom on-chip ram mode 0 low low ??? mode 1 low high expanded disabled enabled * mode 2 high low expanded enabled enabled * mode 3 high high single-chip enabled enabled note: if the rame bit in the system control register (syscr) is cleared to 0, off-chip memory can be accessed instead. modes 1 and 2 are expanded modes that permit access to off-chip memory and peripheral devices. the maximum address space supported by these externally expanded modes is 64k bytes. in mode 3 (single-chip mode), only on-chip rom and ram and the on-chip register field are used. all ports are available for general-purpose input and output. mode 0 is inoperative in the h8/338 series. avoid setting the mode pins to mode 0. in addition, the mode pins must not be changed during mcu operation. rev. 3.0, 09/98, page 54 of 361 3.1.2 mode and system control registers (mdcr and syscr) table 3.2 lists the registers related to the chips operating mode: the system control register (syscr) and mode control register (mdcr). the mode control register indicates the inputs to the mode pins md 1 and md 0 . table 3.2 mode and system control registers name abbreviation read/write address system control register syscr r/w h'ffc4 mode control register mdcr r h'ffc5 3.2 system control register (syscr) ? h'ffc4 bit:76543210 ssby sts2 sts1 sts0 ? nmieg dpme rame initial value: 0 0 0 0 1 0 0 1 read/write: r/w r/w r/w r/w ? r/w r/w * r/w note: do not write 1 in this bit. the system control register (syscr) is an eight-bit register that controls the operation of the chip. bit 7 ? software standby (ssby): enables transition to the software standby mode. for details, see section 14, power-down state. on recovery from software standby mode by an external interrupt, the ssby bit remains set to 1. it can be cleared by writing 0. bit 7 ssby description 0 the sleep instruction causes a transition to sleep mode. (initial value) 1 the sleep instruction causes a transition to software standby mode. rev. 3.0, 09/98, page 55 of 361 bits 6 to 4 ? standby timer select 2 to 0 (sts2 to sts0): these bits select the clock settling time when the chip recovers from the software standby mode by an external interrupt. during the selected time the cpu and on-chip supporting modules continue to stand by. these bits should be set according to the clock frequency so that the settling time is at least 10ms. for specific settings, see section 14.2, system control register: power-down control bits. bit 6 sts2 bit 5 sts1 bit 4 sts0 description 0 0 0 settling time = 8192 states (initial value) 0 0 1 settling time = 16384 states 0 1 0 settling time = 32768 states 0 1 1 settling time = 65536 states 1 ?? settling time = 131072 states bit 3 ? reserved: this bit cannot be modified and is always read as 1. bit 2 ? nmi edge (nmieg): selects the valid edge of the nmi input. bit 2 nmieg description 0 an interrupt is requested on the falling edge of the nmi input. (initial value) 1 an interrupt is requested on the rising edge of the nmi input. bit 1 ? dual-port ram mode enable (dpme): reserved. do not write 1 in this bit. bit 0 ? ram enable (rame): enables or disables the on-chip ram. the rame bit is initialized by a reset, but is not initialized in the software standby mode. bit 0 rame description 0 the on-chip ram is disabled. 1 the on-chip ram is enabled. (initial value) rev. 3.0, 09/98, page 56 of 361 3.3 mode control register (mdcr) ? h'ffc5 bit:76543210 ?????? mds1 mds0 initial value: 1 1 1 0 0 1 ** read/write: r r r r r r r r note: initialized according to md 1 and md 0 inputs. the mode control register (mdcr) is an eight-bit register that indicates the operating mode of the chip. bits 7 to 5 ? reserved: these bits cannot be modified and are always read as 1. bits 4 and 3 ? reserved: these bits cannot be modified and are always read as 0. bit 2 ? reserved: this bit cannot be modified and is always read as 1. bits 1 and 0 ? mode select 1 and 0 (mds1 and mds0): these bits indicate the values of the mode pins (md 1 and md 0 ), thereby indicating the current operating mode of the chip. mds1 corresponds to md 1 and mds0 to md 0 . these bits can be read but not written. when the mode control register is read, the levels at the mode pins (md 1 and md 0 ) are latched in these bits. rev. 3.0, 09/98, page 57 of 361 3.4 address space map figures 3.1 to 3.3 show memory maps of the h8/338, h8/337, and h8/336 in modes 1, 2, and 3. h'ffff h'ff88 h'ff87 h'ff80 h'ff7f h'f780 h'f77f h'0048 h'0047 h'0000 h'ffff h'ff88 h'ff87 h'ff80 h'ff7f h'f780 h'f77f h'ffff h'ff88 h'ff7f h'f780 h'c000 h'bfff h'0048 h'0047 h'0000 h'0048 h'0047 h'0000 mode 1 expanded mode without on-chip rom mode 2 expanded mode with on-chip rom mode 3 single-chip mode vector table on-chip rom, 48k bytes vector table vector table external address space on-chip ram*, 2k bytes note: * external memory can be accessed at these addresses when the rame bit in the system control register syscr) is cleared to 0. h'bfff on-chip rom, 48k bytes external address space on-chip ram*, 2k bytes on-chip ram*, 2k bytes external address space external address space on-chip register field on-chip register field on-chip register field figure 3.1 h8/338 address space map rev. 3.0, 09/98, page 58 of 361 h'ffff h'ff88 h'ff87 h'ff80 h'ff7f h'fb80 h'fb7f h'f780 h'f77f h'0048 h'0047 h'0000 h'ffff h'ff88 h'ff87 h'ff80 h'ff7f h'fb80 h'fb7f h'f780 h'f77f h'ffff h'ff88 h'ff7f h'fb80 h'c000 h'bfff h'8000 h'7fff h'0048 h'0047 h'0000 h'0048 h'0047 h'0000 mode 1 expanded mode without on-chip rom mode 2 expanded mode with on-chip rom mode 3 single-chip mode vector table on-chip rom, 32k bytes h'7fff vector table vector table external address space on-chip rom, 32k bytes reserved*1 external address space reserved*1,*2 reserved*1,*2 on-chip ram*2, 1k byte on-chip ram*2, 1k byte on-chip ram, 1k byte external address space external address space on-chip register field on-chip register field on-chip register field notes: 1. 2. do not access these reserved areas. external memory can be accessed at these addresses when the rame bit in the system control register (syscr) is cleared to 0. figure 3.2 h8/337 address space map rev. 3.0, 09/98, page 59 of 361 h'ffff h'ff88 h'ff87 h'ff80 h'ff7f h'fb80 h'fb7f h'f780 h'f77f h'0048 h'0047 h'0000 h'ffff h'ff88 h'ff87 h'ff80 h'ff7f h'fb80 h'fb7f h'f780 h'f77f h'ffff h'ff88 h'ff7f h'fb80 h'c000 h'bfff h'6000 h'5fff h'0048 h'0047 h'0000 h'0048 h'0047 h'0000 mode 2 expanded mode with on-chip rom vector table on-chip rom, 24k bytes vector table vector table external address space notes: do not access these reserved areas. external memory can be accessed at these addresses when the rame bit in the system control register (syscr) is cleared to 0. 1. 2. h'5fff mode 1 expanded mode without on-chip rom mode 3 single-chip mode on-chip rom, 24k bytes reserved*1 external address space reserved*1,*2 reserved*1,*2 on-chip ram*2, 1k byte on-chip ram*2, 1k byte on-chip ram, 1k byte external address space external address space on-chip register field on-chip register field on-chip register field figure 3.3 h8/336 address space map rev. 3.0, 09/98, page 60 of 361 rev. 3.0, 09/98, page 61 of 361 section 4 exception handling 4.1 overview the h8/338 series recognizes only two kinds of exceptions: interrupts and the reset. table 4.1 indicates their priority and the timing of their hardware exception-handling sequence. table 4.1 hardware exception-handling sequences and priority priority type of exception timing of exception-handling sequence reset the hardware exception-handling sequence begins as soon as res changes from low to high. high low interrupt when an interrupt is requested, the hardware exception-handling sequence begins at the end of the current instruction, or at the end of the current hardware exception-handling sequence. 4.2 reset 4.2.1 overview a reset has the highest exception-handling priority. when the res pin goes low, all current processing stops and the chip enters the reset state. the internal state of the cpu and the registers of the on-chip supporting modules are initialized. when res returns from low to high, the reset exception-handling sequence starts. 4.2.2 reset sequence the reset state begins when res goes low. to ensure correct resetting, at power-on the res pin should be held low for at least 20ms. in a reset during operation, the res pin should be held low for at least 10 system clock cycles. for the pin states during a reset, see appendix c, pin states. when res returns from low to high, hardware carries out the following reset exception- handling sequence. (1) the internal state of the cpu and the registers of the on-chip supporting modules are initialized, and the i bit in the condition code register (ccr) is set to 1. (2) the cpu loads the program counter with the first word in the vector table (stored at addresses h'0000 and h'0001) and starts program execution. the res pin should be held low when power is switched off, as well as when power is switched on. rev. 3.0, 09/98, page 62 of 361 figure 4.1 indicates the timing of the reset sequence in modes 2 and 3. figure 4.2 indicates the timing in mode 1. internal address bus internal read signal internal write signal internal data bus (16 bits) ? res (2) (3) (1) (2) vector fetch (1) reset vector address (h'0000) (2) starting address of program (contents of h'0000 to h'0001) (3) first instruction of program instruction prefetch internal processing figure 4.1 reset sequence (mode 2 or 3, program stored in on-chip rom) rev. 3.0, 09/98, page 63 of 361 a 15 to a 0 rd wr d 7 to d 0 (8 bits) ? res (2) (4) (6) (8) (1) vector fetch (1),(3) reset vector address: (1)=h'0000, (3)=h'0001 (2),(4) starting address of program (contents of reset vector): (2)=upper byte, (4)=lower byte (5),(7) starting address of program: (5)=(2)(4), (7)=(2)(4)+1 (6),(8) first instruction of program: (6)=first byte, (8)=second byte instruction prefetch internal processing (3) (5) (7) figure 4.2 reset sequence (mode 1) rev. 3.0, 09/98, page 64 of 361 4.2.3 disabling of interrupts after reset after a reset, if an interrupt were to be accepted before initialization of the stack pointer (sp: r7), the program counter and condition code register might not be saved correctly, leading to a program crash. to prevent this, all interrupts, including nmi, are disabled immediately after a reset. the first program instruction is therefore always executed. this instruction should initialize the stack pointer (example: mov.w #xx:16, sp). 4.3 interrupts 4.3.1 overview the interrupt sources include nine input pins for external interrupts (nmi, irq 0 to irq 7 ) and 22 internal sources in the on-chip supporting modules. table 4.2 lists the interrupt sources in priority order and gives their vector addresses. when two or more interrupts are requested, the interrupt with highest priority is served first. the features of these interrupts are: nmi has the highest priority and is always accepted. all internal and external interrupts except nmi can be masked by the i bit in the ccr. when the i bit is set to 1, interrupts other than nmi are not accepted. irq 0 to irq 7 can be sensed on the falling edge of the input signal, or level-sensed. the type of sensing can be selected for each interrupt individually. nmi is edge-sensed, and either the rising or falling edge can be selected. all interrupts are individually vectored. the software interrupt-handling routine does not have to determine what type of interrupt has occurred. rev. 3.0, 09/98, page 65 of 361 table 4.2 interrupts interrupt source no. address of entry in vector table priority nmi irq 0 irq 1 irq 2 irq 3 irq 4 irq 5 irq 6 irq 7 3 4 5 6 7 8 9 10 11 h'0006 h'0008 h'000a h'000c h'000e h'0010 h'0012 h'0014 h'0016 ? ? ? ? ? ? ? ? ? h'0007 h'0009 h'000b h'000d h'000f h'0011 h'0013 h'0015 h'0017 high 16-bit free- running timer icia (input capture a) icib (input capture b) icic (input capture c) icid (input capture d) ocia (output compare a) ocib (output compare b) fovi (overflow) 12 13 14 15 16 17 18 h'0018 h'001a h'001c h'001e h'0020 h'0022 h'0024 ? ? ? ? ? ? ? h'0019 h'001b h'001d h'001f h'0021 h'0023 h'0025 8-bit timer 0 cmi0a (compare-match a) cmi0b (compare-match b) ovi0 (overflow) 19 20 21 h'0026 h'0028 h'002a ? ? ? h'0027 h'0029 h'002b 8-bit timer 1 cmi1a (compare-match a) cmi1b (compare-match b) ovi1 (overflow) 22 23 24 h'002c h'002e h'0030 ? ? ? h'002d h'002f h'0031 reserved 25 26 h'0032 h'0034 ? ? h'0033 h'0035 serial communication interface 0 eri0 (receive error) rxi0 (receive end) txi0 (tdr empty) tei0 (tsr empty) 27 28 29 30 h'0036 h'0038 h'003a h'003c ? ? ? ? h'0037 h'0039 h'003b h'003d serial communication interface 1 eri1 (receive error) rxi1 (receive end) txi1 (tdr empty) tei1 (tsr empty) 31 32 33 34 h'003e h'0040 h'0042 h'0044 ? ? ? ? h'003f h'0041 h'0043 h'0045 a/d converter adi (conversion end) 35 h'0046 ? h'0047 low notes: 1. h'0000 and h'0001 contain the reset vector. 2. h'0002 to h'0005 are reserved in the h8/338 series and are not available to the user. rev. 3.0, 09/98, page 66 of 361 4.3.2 interrupt-related registers the interrupt-related registers are the system control register (syscr), irq sense control register (iscr), and irq enable register (ier). table 4.3 registers read by interrupt controller name abbreviation read/write address system control register syscr r/w h'ffc4 irq sense control register iscr r/w h'ffc6 irq enable register ier r/w h'ffc7 system control register (syscr) ? h'ffc4 bit:76543210 ssby sts2 sts1 sts0 ? nmieg dpme rame initial value: 0 0 0 0 1 0 0 1 read/write: r/w r/w r/w r/w ? r/w r/w r/w the valid edge on the nmi line is controlled by bit 2 (nmieg) in the system control register. bit 2 ? nmi edge (nmieg): determines whether a nonmaskable interrupt is generated on the falling or rising edge of the nmi input signal. bit 2 nmieg description 0 an interrupt is generated on the falling edge of nmi . (initial state) 1 an interrupt is generated on the rising edge of nmi . see section 2.2, system control register, for information on the other syscr bits. irq sense control register (iscr) ? h'ffc6 bit:76543210 irq 7 sc irq 6 sc irq 5 sc irq 4 sc irq 3 sc irq 2 sc irq 1 sc irq 0 sc initial value: 0 0 0 0 0 0 0 0 read/write: r/w r/w r/w r/w r/w r/w r/w r/w rev. 3.0, 09/98, page 67 of 361 bits 0 to 7 ? irq 0 to irq 7 sense control (irq 0 sc to irq 7 sc): these bits determine whether irq 0 to irq 7 are level-sensed or sensed on the falling edge. bits 0 to 7 irq 0 sc to irq 7 sc description 0 an interrupt is generated when irq 0 to irq 7 (initial state) inputs are low. 1 an interrupt is generated by the falling edge of the irq 0 to irq 7 inputs. irq enable register (ier) ? h'ffc7 bit:76543210 irq 7 eirq 6 eirq 5 eirq 4 eirq 3 eirq 2 eirq 1 eirq 0 e initial value: 0 0 0 0 0 0 0 0 read/write: r/w r/w r/w r/w r/w r/w r/w r/w bits 0 to 7 ? irq 0 to irq 7 enable (irq 0 e to irq 7 e): these bits enable or disable the irq 0 to irq 7 interrupts individually. bits 0 to 7 irq 0 e to irq 7 e description 0 irq 0 to irq 7 interrupt requests are disabled. (initial state) 1 irq 0 to irq 7 interrupt requests are enabled. when edge sensing is selected (by setting bits irq 0 sc to irq 7 sc to 1), it is possible for an interrupt-handling routine to be executed even though the corresponding enable bit (irq 0 e to irq 7 e) is cleared to 0 and the interrupt is disabled. if an interrupt is requested while the enable bit (irq 0 e to irq 7 e) is set to 1, the request will be held pending until served. if the enable bit is cleared to 0 while the request is still pending, the request will remain pending, although new requests will not be recognized. if the interrupt mask bit (i) in the ccr is cleared to 0, the interrupt-handling routine can be executed even though the enable bit is now 0. if execution of interrupt-handling routines under these conditions is not desired, it can be avoided by using the following procedure to disable and clear interrupt requests. 1. set the i bit to 1 in the ccr, masking interrupts. note that the i bit is set to 1 automatically when execution jumps to an interrupt vector. 2. clear the desired bits from irq 0 e to irq 7 e to 0 to disable new interrupt requests. 3. clear the corresponding irq 0 sc to irq 7 sc bits to 0, then set them to 1 again. pending irqn interrupt requests are cleared when i = 1 in the ccr, irqnsc = 0, and irqne = 0. rev. 3.0, 09/98, page 68 of 361 4.3.3 external interrupts the nine external interrupts are nmi and irq 0 to irq 7 . nmi, irq 0 , irq 1 , and irq 2 can be used to recover from software standby mode. (1) nmi: a nonmaskable interrupt is generated on the rising or falling edge of the nmi input signal regardless of whether the i (interrupt mask) bit is set in the ccr. the valid edge is selected by the nmieg bit in the system control register. the nmi vector number is 3. in the nmi hardware exception-handling sequence the i bit in the ccr is set to 1. (2) irq 0 to irq 7 : these interrupt signals are level-sensed or sensed on the falling edge of the input, as selected by iscr bits irq 0 sc to irq 7 sc. these interrupts can be masked collectively by the i bit in the ccr, and can be enabled and disabled individually by setting and clearing bits irq 0 e to irq 7 e in the irq enable register. when one of these interrupts is accepted, the i bit is set to 1. irq 0 to irq 7 have interrupt vector numbers 4 to 11. they are prioritized in order from irq 7 (low) to irq 0 (high). for details, see table 4.2. interrupts irq 0 to irq 7 do not depend on whether pins irq 0 to irq 7 are input or output pins. when using external interrupts irq 0 to irq 7 , clear the corresponding ddr bits to 0 to set these pins to the input state, and do not use these pins as input or output pins for the timers, serial communication interface, or a/d converter. 4.3.4 internal interrupts twenty-two internal interrupts can be requested by the on-chip supporting modules. each interrupt source has its own vector number, so the interrupt-handling routine does not have to determine which interrupt has occurred. all internal interrupts are masked when the i bit in the ccr is set to 1. when one of these interrupts is accepted, the i bit is set to 1 to mask further interrupts (except nmi ). the vector numbers are 12 to 35. for the priority order, see table 4.2. 4.3.5 interrupt handling interrupts are controlled by an interrupt controller that arbitrates between simultaneous interrupt requests, commands the cpu to start the hardware interrupt exception-handling sequence, and furnishes the necessary vector number. figure 4.3 shows a block diagram of the interrupt controller. rev. 3.0, 09/98, page 69 of 361 irq flag irq 0e adf adie cpu i (ccr) nmi interrupt interrupt controller irq0 interrupt interrupt request vector number adi interrupt priority decision note: * for edge-sensed interrupts, these and gates change to the circuit shown below. * irq0 edge irq0 e sq irq0 flag irq0 interrupt figure 4.3 block diagram of interrupt controller the irq interrupts and interrupts from the on-chip supporting modules all have corresponding enable bits. when the enable bit is cleared to 0, the interrupt signal is not sent to the interrupt controller, so the interrupt is ignored. these interrupts can also all be masked by setting the cpus interrupt mask bit (i) to 1. accordingly, these interrupts are accepted only when their enable bit is set to 1 and the i bit is cleared to 0. the nonmaskable interrupt (nmi) is always accepted, except in the reset state and hardware standby mode. when an nmi or another enabled interrupt is requested, the interrupt controller transfers the interrupt request to the cpu and indicates the corresponding vector number. (when two or more interrupts are requested, the interrupt controller selects the vector number of the interrupt with the highest priority.) when notified of an interrupt request, at the end of the current instruction or current hardware exception-handling sequence, the cpu starts the hardware exception-handling sequence for the interrupt and latches the vector number. figure 4.4 is a flowchart of the interrupt (and reset) operations. figure 4.6 shows the interrupt timing sequence for the case in which the software interrupt-handling routine is in on-chip rom and the stack is in on-chip ram. rev. 3.0, 09/98, page 70 of 361 (1) an interrupt request is sent to the interrupt controller when an nmi interrupt occurs, and when an interrupt occurs on an irq input line or in an on-chip supporting module provided the enable bit of that interrupt is set to 1. (2) the interrupt controller checks the i bit in the ccr and accepts the interrupt request if the i bit is cleared to 0. if the i bit is set to 1 only nmi requests are accepted; other interrupt requests remain pending. (3) among all accepted interrupt requests, the interrupt controller selects the request with the highest priority and passes it to the cpu. other interrupt requests remain pending. (4) when it receives the interrupt request, the cpu waits until completion of the current instruction or hardware exception-handling sequence, then starts the hardware exception- handling sequence for the interrupt and latches the interrupt vector number. (5) in the hardware exception-handling sequence, the cpu first pushes the pc and ccr onto the stack. see figure 4.5. the stacked pc indicates the address of the first instruction that will be executed on return from the software interrupt-handling routine. (6) next the i bit in the ccr is set to 1, masking all further interrupts except nmi. (7) the vector address corresponding to the vector number is generated, the vector table entry at this vector address is loaded into the program counter, and execution branches to the software interrupt-handling routine at the address indicated by that entry. rev. 3.0, 09/98, page 71 of 361 program execution no no no yes no yes yes yes no yes nmi? i = 0? irq 0? irq 1? adi? reset i 1 interrupt requested? pending latch vector no. save pc save ccr read vector address branch to software interrupt-handling routine yes figure 4.4 hardware interrupt-handling sequence rev. 3.0, 09/98, page 72 of 361 sp-4 sp-3 sp-2 sp-1 sp(r7) stack area sp(r7) sp+1 sp+2 sp+3 sp+4 even address after interrupt is accepted pushed onto stack before interrupt is accepted ccr ccr * pc h pc l legend: pc h pc l ccr sp program counter (upper byte) program counter (lower byte) condition code register stack pointer the pc contains the address of the first instruction executed after return. registers must be saved and restored by word access at an even address. * ignored on return. notes: 1. 2. figure 4.5 usage of stack in interrupt handling rev. 3.0, 09/98, page 73 of 361 internal address bus internal read signal internal write signal internal 16-bit data bus ? interrupt request signal (2) (4) (1) (7) (9) (10) (8) (6) (5) (3) (1) (9) stack vector fetch instruction prefetch address (pushed on stack. instruction is executed on return from interrupt-handling routine.) instruction code (not executed) instruction prefetch address (not executed) sp-2 (1) (2) (4) (3) (5) sp-4 ccr address of vector table entry vector table entry (address of first instruction of interrupt-handling routine) first instruction of interrupt-handling routine (6) (7) (8) (9) (10) interrupt priority decision. wait for end of instruction. instruction fetch (first instruction of interrupt-handling routine) internal processing internal processing instruction fetch interrupt accepted figure 4.6 timing of interrupt sequence rev. 3.0, 09/98, page 74 of 361 4.3.6 interrupt response time table 4.4 indicates the number of states that elapse from an interrupt request signal until the first instruction of the software interrupt-handling routine is executed. since on-chip memory is accessed 16 bits at a time, very fast interrupt service can be obtained by placing interrupt-handling routines in on-chip rom and the stack in on-chip ram. table 4.4 number of states before interrupt service number of states no. reason for wait on-chip memory external memory 1 interrupt priority decision 2 * 3 2 * 3 2 wait for completion of current instruction * 1 1 to 13 5 to 17 * 2 3 save pc and ccr 4 12 * 2 4 fetch vector 2 6 * 2 5 fetch instruction 4 12 * 2 6 internal processing 4 4 total 17 to 29 41 to 53 * 2 notes: 1. these values do not apply if the current instruction is eepmov. 2. if wait states are inserted in external memory access, add the number of wait states. 3. 1 for internal interrupts. rev. 3.0, 09/98, page 75 of 361 4.3.7 precaution note that the following type of contention can occur in interrupt handling. contention between interrupt request and disable: when software clears the enable bit of an interrupt to 0 to disable the interrupt, the interrupt becomes disabled after execution of the clearing instruction. if an enable bit is cleared by a bclr or mov instruction, for example, and the interrupt is requested during execution of that instruction, at the instant when the instruction ends the interrupt is still enabled, so after execution of the instruction, the hardware exception- handling sequence is executed for the interrupt. if a higher-priority interrupt is requested at the same time, however, the hardware exception-handling sequence is executed for the higher-priority interrupt and the interrupt that was disabled is ignored. similar considerations apply when an interrupt request flag is cleared to 0. figure 4.7 shows an example in which the ociae bit is cleared to 0. ? internal address bus ociae ocia interrupt handling ocia interrupt signal ocfa cpu write cycle to tier internal write signal tier address figure 4.7 contention between interrupt and disabling instruction the above contention does not occur if the enable bit or flag is cleared to 0 while the interrupt mask bit (i) is set to 1. rev. 3.0, 09/98, page 76 of 361 4.4 note on stack handling in word access, the least significant bit of the address is always assumed to be 0. the stack is always accessed by word access. care should be taken to keep an even value in the stack pointer (general register r7). use the push and pop (or mov.w rn, @ - sp and mov.w @sp+, rn) instructions to push and pop registers on the stack. setting the stack pointer to an odd value can cause programs to crash. figure 4.8 shows an example of damage caused when the stack pointer contains an odd address. sp legend: pch pcl r1l sp : upper byte of program counter : lower byte of program counter : general register : stack pointer h'fecc h'fecd h'fecf r1l pc l sp pc h pc l sp mov.b r1l, @-r7 bsr instruction h'fecf set in sp pc is improperly stored beyond top of stack pch is lost figure 4.8 example of damage caused by setting an odd address in r7 although the ccr consists of only one byte, it is treated as word data when pushed on the stack. in the hardware interrupt exception-handling sequence, two identical ccr bytes are pushed onto the stack to make a complete word. when popped from the stack by an rte instruction, the ccr is loaded from the byte stored at the even address. the byte stored at the odd address is ignored. rev. 3.0, 09/98, page 77 of 361 section 5 clock pulse generator 5.1 overview the h8/338 series has a built-in clock pulse generator (cpg) consisting of an oscillator circuit, a system ( f ) clock divider, and a prescaler. the prescaler generates clock signals for the on-chip supporting modules. 5.1.1 block diagram xtal extal ?/2 to ?/4096 prescaler divider 2 ? cpg oscillator circuit figure 5.1 block diagram of clock pulse generator rev. 3.0, 09/98, page 78 of 361 5.2 oscillator circuit if an external crystal is connected across the extal and xtal pins, the on-chip oscillator circuit generates a clock signal for the system clock divider. alternatively, an external clock signal can be applied to the extal pin. (1) connecting an external crystal ? circuit configuration: an external crystal can be connected as in the example in figure 5.2. an at-cut parallel resonating crystal should be used. extal xtal c l1 c l1 = c l2 = 10 to 22pf c l2 figure 5.2 connection of crystal oscillator (example) - crystal oscillator: the external crystal should have the characteristics listed in table 5.1. table 5.1 external crystal parameters frequency (mhz) 2 4 8 12 16 20 rs max ( w ) 500 120 60 40 30 20 c0 (pf) 7 pf max c l c 0 xtal extal lr s at-cut parallel resonating crystal figure 5.3 equivalent circuit of external crystal rev. 3.0, 09/98, page 79 of 361 ? note on board design: when an external crystal is connected, other signal lines should be kept away from the crystal circuit to prevent induction from interfering with correct oscillation. see figure 5.4. the crystal and its load capacitors should be placed as close as possible to the xtal and extal pins. not allowed signal a signal b h8/337 xtal extal c l1 c l2 (example of h8/337) figure 5.4 notes on board design around external crystal rev. 3.0, 09/98, page 80 of 361 (2) input of external clock signal ? circuit configuration: an external clock signal can be input as shown in the examples in figure 5.5. in example (b) in figure 5.5, the external clock signal should be kept high during standby. extal xtal external clock input 74hc04 (b) extal xtal external clock input open (a) figure 5.5 external clock input (example) - external clock input frequency double the system clock ( f ) frequency duty factor 45% to 55% 5.3 system clock divider the system clock divider divides the crystal oscillator or external clock frequency by 2 to create the system clock ( f ). rev. 3.0, 09/98, page 81 of 361 section 6 i/o ports 6.1 overview the h8/338 series has nine parallel i/o ports, including: six 8-bit input/output ports-ports 1, 2, 3, 4, 6, and 9 one 8-bit input port-port 7 one 7-bit input/output port-port 8 one 3-bit input/output port-port 5 ports 1, 2, and 3 have programmable input pull-up transistors. ports 1 to 6, 8, and 9 can drive a darlington pair. ports 1 to 4, 6, and 9 can drive one ttl load and a 90pf capacitive load. ports 5 and 8 can drive one ttl load and a 30pf capacitive load. ports 1 and 2 can drive leds (10ma current sink). input and output are memory-mapped. the cpu views each port as a data register (dr) located in the register field at the high end of the address space. each port (except port 7) also has a data direction register (ddr) which determines which pins are used for input and which for output. output: to send data to an output port, the cpu selects output in the data direction register and writes the desired data in the data register, causing the data to be held in a latch. the latch output drives the pin through a buffer amplifier. if the cpu reads the data register of an output port, it obtains the data held in the latch rather than the actual level of the pin. input: to read data from an i/o port, the cpu selects input in the data direction register and reads the data register. this causes the input logic level at the pin to be placed directly on the internal data bus. there is no intervening input latch. the data direction registers are write-only registers; their contents are invisible to the cpu. if the cpu reads a data direction register all bits are read as 1, regardless of their true values. care is required if bit manipulation instructions are used to set and clear the data direction bits. see the note on bit manipulation instructions in section 3.5.5, bit manipulations. auxiliary functions: in addition to their general-purpose input/output functions, all of the i/o ports have auxiliary functions. most of the auxiliary functions are software-selectable and must be enabled by setting bits in control registers. when selected, an auxiliary function usually replaces the general-purpose input/output function, but in some cases both functions can operate simultaneously. table 6.1 summarizes the functions of the ports. rev. 3.0, 09/98, page 82 of 361 table 6.1 port functions expanded modes single-chip mode port description pins mode 1 mode 2 mode 3 port 1 8-bit input-output port can drive leds input pull-ups p1 7 to p1 0 / a 7 to a 0 address output (low) general input when ddr = 0 (initial state) address output (low) when ddr = 1 general input/ output port 2 8-bit input-output port can drive leds input pull-ups p2 7 to p2 0 / a 15 to a 8 address output (high) general input when ddr = 0 (initial state) address output (high) when ddr = 1 general input/ output port 3 8-bit input-output port input pull-ups p3 7 to p3 0 / d 7 to d 0 data bus data bus general input/ output port 4 8-bit input-output port p4 7 to p4 0 general input/output, 8-bit timer 0/1 input/output (tmci 0 , tmo 0 , tmri 0 , tmci 1 , tmo 1 , tmri 1 ), or pwm timer 0/1 output (pw 0 , pw 1 ) port 5 3-bit input-output port p5 2 to p5 0 general input/output or serial communication interface 0 input/output (txd 0 , rxd 0 , sck 0 ) port 6 8-bit input-output port p6 7 to p6 0 general input/output, 16-bit free-running timer input/output (ftci, ftoa, ftob, ftia, ftib, ftic, ftid), or external interrupt input ( irq 6 , irq 7 ) rev. 3.0, 09/98, page 83 of 361 table 6.1 port functions (cont) expanded modes single-chip mode port description pins mode 1 mode 2 mode 3 port 7 ? 8-bit input port p7 7 to p7 0 general input, analog input to a/d converter (an 7 to an 0 ), or analog output from d/a converter (da 0 , da 1 ) port 8 ? 7-bit input-output port p8 6 /sck 1 / irq 5 p8 5 /rxd 1 / irq 4 p8 4 /txd 1 / irq 3 general input/output, serial communication interface 1 input/output (txd 1 , rxd 1 , sck 1 ), or external interrupt input ( irq 3 , irq 4 , irq 5 ) p8 3 to p8 0 general input/output port 9 ? 8-bit input-output port p9 7 / wait wait input general input/ output p9 6 / f system clock output general input when ddr = 0 (initial state) system clock output when ddr = 1 p9 5 / as as output p9 4 / wr wr output general input/ output p9 3 / rd rd output p9 2 / irq 0 p9 1 / irq 1 general input/output or external interrupt input ( irq 0 , irq 1 ) p9 0 / adtrg / irq 2 general input/output, a/d converter trigger input ( adtrg ), or external interrupt input ( irq 2 ) rev. 3.0, 09/98, page 84 of 361 6.2 port 1 port 1 is an 8-bit input/output port that also provides the low bits of the address bus. the function of port 1 depends on the mcu mode as indicated in table 6.2. table 6.2 functions of port 1 mode 1 mode 2 mode 3 address bus (low) (a 7 to a 0 ) input port or address bus (low) (a 7 to a 0 ) * input/output port note: depending on the bit settings in the data direction register: 0 ? input pin; 1 ? address pin pins of port 1 can drive a single ttl load and a 90pf capacitive load when they are used as output pins. they can also drive light-emitting diodes and a darlington pair. when they are used as input pins, they have programmable mos transistor pull-ups. table 6.3 details the port 1 registers. table 6.3 port 1 registers name abbreviation read/write initial value address port 1 data direction register p1ddr w h'ff (mode 1) h'00 (modes 2 and 3) h'ffb0 port 1 data register p1dr r/w h'00 h'ffb2 port 1 input pull-up control register p1pcr r/w h'00 h'ffac port 1 data direction register (p1ddr) ? h'ffb0 bit 76543210 p1 7 ddr p1 6 ddr p1 5 ddr p1 4 ddr p1 3 ddr p1 2 ddr p1 1 ddr p1 0 ddr mode 1 initial value 1 1 1 1 1 1 1 1 read/write ???????? modes 2 and 3 initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w p1ddr is an 8-bit register that selects the direction of each pin in port 1. a pin functions as an output pin if the corresponding bit in p1ddr is set to 1, and as an input pin if the bit is cleared to 0. rev. 3.0, 09/98, page 85 of 361 port 1 data register (p1dr) ? h'ffb2 bit:76543210 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 initial value: 0 0 0 0 0 0 0 0 read/write: r/w r/w r/w r/w r/w r/w r/w r/w p1dr is an 8-bit register containing the data for pins p1 7 to p1 0 . when the cpu reads p1dr, for output pins it reads the value in the p1dr latch, but for input pins, it obtains the logic level directly from the pin, bypassing the p1dr latch. port 1 input pull-up control register (p1pcr) ? h'ffac bit:76543210 p1 7 pcr p1 6 pcr p1 5 pcr p1 4 pcr p1 3 pcr p1 2 pcr p1 1 pcr p1 0 pcr initial value: 0 0 0 0 0 0 0 0 read/write: r/w r/w r/w r/w r/w r/w r/w r/w p1pcr is an 8-bit readable/writable register that controls the input pull-up transistors in port 1. if a bit in p1ddr is cleared to 0 (designating input) and the corresponding bit in p1pcr is set to 1, the input pull-up transistor for that bit is turned on. mode 1: in mode 1 (expanded mode without on-chip rom), port 1 is automatically used for address output. the port 1 data direction register is unwritable. all bits in p1ddr are automatically set to 1 and cannot be cleared to 0. mode 2: in mode 2 (expanded mode with on-chip rom), the usage of port 1 can be selected on a pin-by-pin basis. a pin is used for general-purpose input if its data direction bit is cleared to 0, or for address output if its data direction bit is set to 1. mode 3: in the single-chip mode port 1 is a general-purpose input/output port. reset: a reset clears p1ddr, p1dr, and p1pcr to all 0, placing all pins in the input state with the pull-up transistors off. in mode 1, when the chip comes out of reset, p1ddr is set to all 1. hardware standby mode: all pins are placed in the high-impedance state with the pull-up transistors off. p1dr and p1pcr are initialized to h'00. in modes 2 and 3, p1ddr is initialized to h'00. software standby mode: in the software standby mode, p1ddr, p1dr, and p1pcr remain in their previous state. address output pins are low. general-purpose output pins continue to output the data in p1dr. rev. 3.0, 09/98, page 86 of 361 input pull-up transistors: port 1 has built-in programmable input pull-up transistors that are available in modes 2 and 3. the pull-up for each bit can be turned on and off individually. to turn on an input pull-up in mode 2 or 3, set the corresponding p1pcr bit to 1 and clear the corresponding p1ddr bit to 0. p1pcr is cleared to h'00 by a reset and in the hardware standby mode, turning all input pull-ups off. in software standby mode, the previous state is maintained. table 6.4 indicates the states of the input pull-up transistors in each operating mode. table 6.4 states of input pull-up transistors (port 1) mode reset hardware standby software standby other operating modes 1 off off off off 2 off off on/off on/off 3 off off on/off on/off notes: off: the input pull-up transistor is always off. on/off: the input pull-up transistor is on if p1pcr = 1 and p1ddr = 0, but off otherwise. rev. 3.0, 09/98, page 87 of 361 figure 6.1 shows a schematic diagram of port 1. p1 n hardware standby mode 3 mode 1 or 2 rp1 reset reset mode 1 reset wp1 wp1d wp1p r r s r q q q d d d p1 n dr p1 n ddr p1 n pcr c c c * rp1p wp1p: wp1d: wp1: rp1p : rp1: n = 0 to 7 note: * set-priority write port 1 pcr write port 1 ddr write port 1 read port 1 pcr read port 1 internal data bus internal address bus figure 6.1 port 1 schematic diagram rev. 3.0, 09/98, page 88 of 361 6.3 port 2 port 2 is an 8-bit input/output port that also provides the high bits of the address bus. the function of port 2 depends on the mcu mode as indicated in table 6.5. table 6.5 functions of port 2 mode 1 mode 2 mode 3 address bus (high) (a 15 to a 8 ) input port or address bus (high) (a 15 to a 8 ) * input/output port note: depending on the bit settings in the data direction register: 0 ? input pin; 1 ? address pin pins of port 2 can drive a single ttl load and a 90pf capacitive load when they are used as output pins. they can also drive light-emitting diodes and a darlington pair. when they are used as input pins, they have programmable mos transistor pull-ups. table 6.6 details the port 2 registers. table 6.6 port 2 registers name abbreviation read/write initial value address port 2 data direction register p2ddr w h'ff (mode 1) h'00 (modes 2 and 3) h'ffb1 port 2 data register p2dr r/w h'00 h'ffb3 port 2 input pull-up control register p2pcr r/w h'00 h'ffad port 2 data direction register (p2ddr) ? h'ffb1 bit 76543210 p2 7 ddr p2 6 ddr p2 5 ddr p2 4 ddr p2 3 ddr p2 2 ddr p2 1 ddr p2 0 ddr mode 1 initial value 1 1 1 1 1 1 1 1 read/write ???????? modes 2 and 3 initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w p2ddr is an 8-bit register that selects the direction of each pin in port 2. a pin functions as an output pin if the corresponding bit in p2ddr is set to 1, and as an input pin if the bit is cleared to 0. rev. 3.0, 09/98, page 89 of 361 port 2 data register (p2dr) ? h'ffb3 bit:76543210 p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 initial value: 0 0 0 0 0 0 0 0 read/write: r/w r/w r/w r/w r/w r/w r/w r/w p2dr is an 8-bit register containing the data for pins p2 7 to p2 0 . when the cpu reads p2dr, for output pins it reads the value in the p2dr latch, but for input pins, it obtains the logic level directly from the pin, bypassing the p2dr latch. port 2 input pull-up control register (p2pcr) ? h'ffad bit:76543210 p2 7 pcr p2 6 pcr p2 5 pcr p2 4 pcr p2 3 pcr p2 2 pcr p2 1 pcr p2 0 pcr initial value: 0 0 0 0 0 0 0 0 read/write: r/w r/w r/w r/w r/w r/w r/w r/w p2pcr is an 8-bit readable/writable register that controls the input pull-up transistors in port 2. if a bit in p2ddr is cleared to 0 (designating input) and the corresponding bit in p2pcr is set to 1, the input pull-up transistor for that bit is turned on. mode 1: in mode 1 (expanded mode without on-chip rom), port 2 is automatically used for address output. the port 2 data direction register is unwritable. all bits in p2ddr are automatically set to 1 and cannot be cleared to 0. mode 2: in mode 2 (expanded mode with on-chip rom), the usage of port 2 can be selected on a pin-by-pin basis. a pin is used for general-purpose input if its data direction bit is cleared to 0, or for address output if its data direction bit is set to 1. mode 3: in the single-chip mode port 2 is a general-purpose input/output port. reset: a reset clears p2ddr, p2dr, and p2pcr to all 0, placing all pins in the input state with the pull-up transistors off. in mode 1, when the chip comes out of reset, p2ddr is set to all 1. hardware standby mode: all pins are placed in the high-impedance state with the pull-up transistors off. p2dr and p2pcr are initialized to h'00. in modes 2 and 3, p2ddr is initialized to h'00. software standby mode: in the software standby mode, p2ddr, p2dr, and p2pcr remain in their previous state. address output pins are low. general-purpose output pins continue to output the data in p2dr. rev. 3.0, 09/98, page 90 of 361 input pull-up transistors: port 2 has built-in programmable input pull-up transistors that are available in modes 2 and 3. the pull-up for each bit can be turned on and off individually. to turn on an input pull-up in mode 2 or 3, set the corresponding p2pcr bit to 1 and clear the corresponding p2ddr bit to 0. p2pcr is cleared to h'00 by a reset and in the hardware standby mode, turning all input pull-ups off. in software standby mode, the previous state is maintained. table 6.7 indicates the states of the input pull-up transistors in each operating mode. table 6.7 states of input pull-up transistors (port 2) mode reset hardware standby software standby other operating modes 1 off off off off 2 off off on/off on/off 3 off off on/off on/off notes: off: the input pull-up transistor is always off. on/off: the input pull-up transistor is on if p2pcr = 1 and p2ddr = 0, but off otherwise. rev. 3.0, 09/98, page 91 of 361 figure 6.2 shows a schematic diagram of port 2. p2 n hardware standby mode 3 mode 1 or 2 rp2 reset reset mode 1 reset wp2 wp2d wp2p r r s r q q q d d d p2 n dr p2n ddr p2 n pcr c c c * rp2p wp2p: wp2d: wp2: rp2p : rp2: n = 0 to 7 note: * set-priority write port 2 pcr write port 2 ddr write port 2 read port 2 pcr read port 2 internal data bus internal address bus figure 6.2 port 2 schematic diagram rev. 3.0, 09/98, page 92 of 361 6.4 port 3 port 3 is an 8-bit input/output port that also provides the external data bus. the function of port 3 depends on the mcu mode as indicated in table 6.8. table 6.8 functions of port 3 mode 1 mode 2 mode 3 data bus data bus input/output port pins of port 3 can drive a single ttl load and a 90pf capacitive load when they are used as output pins. they can also drive a darlington pair. when they are used as input pins, they have programmable mos transistor pull-ups. table 6.9 details the port 3 registers. table 6.9 port 3 registers name abbreviation read/write initial value address port 3 data direction register p3ddr w h'00 h'ffb4 port 3 data register p3dr r/w h'00 h'ffb6 port 3 input pull-up control register p3pcr r/w h'00 h'ffae port 3 data direction register (p3ddr) ? h'ffb4 bit:76543210 p3 7 ddr p3 6 ddr p3 5 ddr p3 4 ddr p3 3 ddr p3 2 ddr p3 1 ddr p3 0 ddr initial value: 0 0 0 0 0 0 0 0 read/write: w w w w w w w w p3ddr is an 8-bit register that selects the direction of each pin in port 3. a pin functions as an output pin if the corresponding bit in p3ddr is set to 1, and as an input pin if the bit is cleared to 0. port 3 data register (p3dr) ? h'ffb6 bit:76543210 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 initial value: 0 0 0 0 0 0 0 0 read/write: r/w r/w r/w r/w r/w r/w r/w r/w rev. 3.0, 09/98, page 93 of 361 p3dr is an 8-bit register containing the data for pins p3 7 to p3 0 . when the cpu reads p3dr, for output pins it reads the value in the p3dr latch, but for input pins, it obtains the logic level directly from the pin, bypassing the p3dr latch. port 3 input pull-up control register (p3pcr) ? h'ffae bit:76543210 p3 7 pcr p3 6 pcr p3 5 pcr p3 4 pcr p3 3 pcr p3 2 pcr p3 1 pcr p3 0 pcr initial value: 0 0 0 0 0 0 0 0 read/write: r/w r/w r/w r/w r/w r/w r/w r/w p3pcr is an 8-bit readable/writable register that controls the input pull-up transistors in port 3. if a bit in p3ddr is cleared to 0 (designating input) and the corresponding bit in p3pcr is set to 1, the input pull-up transistor for that bit is turned on. modes 1 and 2: in the expanded modes, port 3 is automatically used as the data bus. the values in p3ddr, p3dr, and p3pcr are ignored. mode 3: in the single-chip mode, port 3 can be used as a general-purpose input/output port. reset and hardware standby mode: a reset or entry to the hardware standby mode clears p3ddr, p3dr, and p3pcr to all 0. all pins are placed in the high-impedance state with the pull-up transistors off. software standby mode: in the software standby mode, p3ddr, p3dr, and p3pcr remain in their previous state. in modes 1 and 2, all pins are placed in the data input (high-impedance) state. in mode 3, all pins remain in their previous input or output state. input pull-up transistors: port 3 has built-in programmable input pull-up transistors that are available in mode 3. the pull-up for each bit can be turned on and off individually. to turn on an input pull-up in mode 3, set the corresponding p3pcr bit to 1 and clear the corresponding p3ddr bit to 0. p3pcr is cleared to h'00 by a reset and in the hardware standby mode, turning all input pull-ups off. in software standby mode, the previous state is maintained. rev. 3.0, 09/98, page 94 of 361 table 6.10 indicates the states of the input pull-up transistors in each operating mode. table 6.10 states of input pull-up transistors (port 3) mode reset hardware standby software standby other operating modes 1 off off off off 2 off off off off 3 off off on/off on/off notes: off: the input pull-up transistor is always off. on/off: the input pull-up transistor is on if p3pcr = 1 and p3ddr = 0, but off otherwise. rev. 3.0, 09/98, page 95 of 361 figure 6.3 shows a schematic diagram of port 3. p3 n reset reset reset wp3 wp3d wp3p r r r q q q d d d p3 n dr p3 n ddr p3 n pcr c c c rp3 external address write mode 1 or 2 external address read wp3p: wp3d: wp3: rp3p : rp3: n = 0 to 7 write port 3 pcr write port 3 ddr write port 3 read port 3 pcr read port 3 mode 3 mode 3 rp3p mode 3 internal data bus figure 6.3 port 3 schematic diagram rev. 3.0, 09/98, page 96 of 361 6.5 port 4 port 4 is an 8-bit input/output port that also provides the input and output pins for the 8-bit timers and the output pins for the pwm timers. the pin functions depend on control bits in the control registers of the timers. pins not used by the timers are available for general-purpose input/output. table 6.11 lists the pin functions, which are the same in both the expanded and single-chip modes. table 6.11 port 4 pin functions (modes 1 to 3) usage pin functions i/o port p4 0 p4 1 p4 2 p4 3 p4 4 p4 5 p4 6 p4 7 timer tmci 0 tmo 0 tmri 0 tmci 1 tmo 1 tmri 1 pw 0 pw 1 see section 7, 8-bit timers and section 8, pwm timers, for details of the timer control bits. pins of port 4 can drive a single ttl load and a 90pf capacitive load when they are used as output pins. they can also drive a darlington pair. table 6.12 details the port 4 registers. table 6.12 port 4 registers name abbreviation read/write initial value address port 4 data direction register p4ddr w h'00 h'ffb5 port 4 data register p4dr r/w h'00 h'ffb7 port 4 data direction register (p4ddr) ? h'ffb5 bit:76543210 p4 7 ddr p4 6 ddr p4 5 ddr p4 4 ddr p4 3 ddr p4 2 ddr p4 1 ddr p4 0 ddr initial value: 0 0 0 0 0 0 0 0 read/write: w w w w w w w w p4ddr is an 8-bit register that selects the direction of each pin in port 4. a pin functions as an output pin if the corresponding bit in p4ddr is set to 1, and as an input pin if the bit is cleared to 0. rev. 3.0, 09/98, page 97 of 361 port 4 data register (p4dr) ? h'ffb7 bit:76543210 p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 initial value: 0 0 0 0 0 0 0 0 read/write: r/w r/w r/w r/w r/w r/w r/w r/w p4dr is an 8-bit register containing the data for pins p4 7 to p4 0 . when the cpu reads p4dr, for output pins (p4ddr = 1) it reads the value in the p4dr latch, but for input pins (p4ddr = 0), it obtains the logic level directly from the pin, bypassing the p4dr latch. this also applies to pins used for timer input or output. pins p4 0 , p4 2 , p4 3 , and p4 5 : as indicated in table 6.11, these pins can be used for general- purpose input or output, or input of 8-bit timer clock and reset signals. when a pin is used for timer signal input, its p4ddr bit should normally be cleared to 0; otherwise the timer will receive the value in p4dr. pins p4 1 , p4 4 , p4 6 , and p4 7 : as indicated in table 6.11, these pins can be used for general- purpose input or output, or for 8-bit timer output (p4 1 and p4 4 ) or pwm timer output (p4 6 and p4 7 ). pins used for timer output are unaffected by the values in p4ddr and p4dr. reset and hardware standby mode: a reset or entry to the hardware standby mode clears p4ddr and p4dr to all 0 and makes all pins into input port pins. software standby mode: in the software standby mode, the control registers of the 8-bit and pwm timers are initialized but p4ddr and p4dr remain in their previous states. all pins become input or output port pins depending on the setting of p4ddr. output pins output the values in p4dr. rev. 3.0, 09/98, page 98 of 361 figures 6.4 (a) and 6.4 (b) show schematic diagrams of port 4. p4 n rp4 reset internal data bus reset wp4 wp4d r r q q d d p4 n dr p4 n ddr c c wp4d: wp4: rp4: n = 0, 2, 3, 5 write port 4 ddr write port 4 read port 4 8-bit timer module counter reset input counter clock input figure 6.4 (a) port 4 schematic diagram (pins p4 0 , p4 2 , p4 3 , and p4 5 ) rev. 3.0, 09/98, page 99 of 361 rp4 reset reset wp4 wp4d r r q q d d p4 n dr p4 n ddr c c wp4d: wp4: rp4: n = 1, 4, 6, 7 write port 4 ddr write port 4 read port 4 8-bit timer module, pwm timer module output enable 8-bit timer output or pwm timer output p4 n internal data bus figure 6.4 (b) port 4 schematic diagram (pins p4 1 , p4 4 , p4 6 , and p4 7 ) rev. 3.0, 09/98, page 100 of 361 6.6 port 5 port 5 is a 3-bit input/output port that also provides the input and output pins for serial communi- cation interface 0 (sci0). the pin functions depend on control bits in the serial control register (scr). pins not used for serial communication are available for general-purpose input/output. table 6.13 lists the pin functions, which are the same in both the expanded and single-chip modes. table 6.13 port 5 pin functions (modes 1 to 3) usage pin functions i/o port p5 0 p5 1 p5 2 serial communication interface 0 txd 0 rxd 0 sck 0 see section 9, serial communication interface, for details of the serial control bits. pins used by the serial communication interface are switched between input and output without regard to the values in the data direction register. pins of port 5 can drive a single ttl load and a 30pf capacitive load when they are used as output pins. they can also drive a darlington pair. table 6.14 details the port 5 registers. table 6.14 port 5 registers name abbreviation read/write initial value address port 5 data direction register p5ddr w h'f8 h'ffb8 port 5 data register p5dr r/w h'f8 h'ffba port 5 data direction register (p5ddr) ? h'ffb8 bit:76543210 ????? p5 2 ddr p5 1 ddr p5 0 ddr initial value: 1 1 1 1 1 0 0 0 read/write: ????? www p5ddr is an 8-bit register that selects the direction of each pin in port 5. a pin functions as an output pin if the corresponding bit in p5ddr is set to 1, and as an input pin if the bit is cleared to 0. rev. 3.0, 09/98, page 101 of 361 port 5 data register (p5dr) ? h'ffba bit:76543210 ????? p5 2 p5 1 p5 0 initial value: 1 1 1 1 1 0 0 0 read/write: ????? r/w r/w r/w p5dr is an 8-bit register containing the data for pins p5 2 to p5 0 . when the cpu reads p5dr, for output pins (p5ddr = 1) it reads the value in the p5dr latch, but for input pins (p5ddr = 0), it obtains the logic level directly from the pin, bypassing the p5dr latch. this also applies to pins used for serial communication. pin p5 0 : this pin can be used for general-purpose input or output, or for output of serial transmit data (txd 0 ). when used for txd 0 output, this pin is unaffected by the values in p5ddr and p5dr. pin p5 1 : this pin can be used for general-purpose input or output, or for input of serial receive data (rxd 0 ). when used for rxd 0 input, this pin is unaffected by p5ddr and p5dr. pin p5 2 : this pin can be used for general-purpose input or output, or for serial clock input or output (sck 0 ). when used for sck 0 input or output, this pin is unaffected by p5ddr and p5dr. reset and hardware standby mode: a reset or entry to the hardware standby mode makes all pins of port 5 into input port pins. software standby mode: in the software standby mode, the serial control register is initialized but p5ddr and p5dr remain in their previous states. all pins become input or output port pins depending on the setting of p5ddr. output pins output the values in p5dr. rev. 3.0, 09/98, page 102 of 361 figures 6.5 (a) to 6.5 (c) show schematic diagrams of port 5. rp5 reset reset internal data bus wp5 wp5d r r q q d d p5 0 dr p5 0 ddr c c wp5d: wp5: rp5: write port 5 ddr write port 5 read port 5 sci module transmit enable transmit data p5 0 figure 6.5 (a) port 5 schematic diagram (pin p5 0 ) rev. 3.0, 09/98, page 103 of 361 p5 1 rp5 reset reset wp5 wp5d r r q q d d p5 1 dr p5 1ddr c c wp5d: wp5: rp5: write port 5 ddr write port 5 read port 5 sci module receive enable internal data bus receive data figure 6.5 (b) port 5 schematic diagram (pin p5 1 ) rev. 3.0, 09/98, page 104 of 361 rp5 reset reset wp5 wp5d r r q q d d p5 2 dr p5 2 ddr c c wp5d: wp5: rp5: write port 5 ddr write port 5 read port 5 sci module internal data bus clock input enable clock output enable clock output clock input p5 2 figure 6.5 (c) port 5 schematic diagram (pin p5 2 ) rev. 3.0, 09/98, page 105 of 361 6.7 port 6 port 6 is an 8-bit input/output port that also provides the input and output pins for the free-running timer and the irq 6 and irq 7 input/output pins. the pin functions depend on control bits in the free-running timer control registers, and on bit 6 or 7 of the interrupt enable register. pins not used for timer or interrupt functions are available for general-purpose input/output. table 6.15 lists the pin functions, which are the same in both the expanded and single-chip modes. table 6.15 port 6 pin functions usage pin functions (modes 1 to 3) i/o port p6 0 p6 1 p6 2 p6 3 p6 4 p6 5 p6 6 p6 7 timer/interrupt ftci ftoa ftia ftib ftic ftid ftob/ irq 6 irq 7 see section 4 exception handling and section 6, 16-bit free-running timer for details of the free-running timer and interrupts. pins of port 6 can drive a single ttl load and a 90pf capacitive load when they are used as output pins. they can also drive a darlington pair. table 6.16 details the port 6 registers. table 6.16 port 6 registers name abbreviation read/write initial value address port 6 data direction register p6ddr w h'00 h'ffb9 port 6 data register p6dr r/w h'00 h'ffbb port 6 data direction register (p6ddr) ? h'ffb9 bit:76543210 p6 7 ddr p6 6 ddr p6 5 ddr p6 4 ddr p6 3 ddr p6 2 ddr p6 1 ddr p6 0 ddr initial value: 0 0 0 0 0 0 0 0 read/write: w w w w w w w w p6ddr is an 8-bit register that selects the direction of each pin in port 6. a pin functions as an output pin if the corresponding bit in p6ddr is set to 1, and as an input pin if the bit is cleared to 0. rev. 3.0, 09/98, page 106 of 361 port 6 data register (p6dr) ? h'ffbb bit:76543210 p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 initial value: 0 0 0 0 0 0 0 0 read/write: r/w r/w r/w r/w r/w r/w r/w r/w p6dr is an 8-bit register containing the data for pins p6 7 to p6 0 . when the cpu reads p6dr, for output pins (p6ddr = 1) it reads the value in the p6dr latch, but for input pins (p6ddr = 0), it obtains the logic level directly from the pin, bypassing the p6dr latch. this also applies to pins used for input and output of timer and interrupt signals. pins p6 0 , p6 2 , p6 3 , p6 4 and p6 5 : as indicated in table 6.15, these pins can be used for general- purpose input or output, or for input of free-running timer clock and input capture signals. when a pin is used for free-running timer input, its p6ddr bit should be cleared to 0; otherwise the free-running timer will receive the value in p6dr. pin p6 1 : this pin can be used for general-purpose input or output, or for the output compare a signal (ftoa) of the free-running timer. when used for ftoa output, this pin is unaffected by the values in p6ddr and p6dr. pin p6 6 : this pin can be used for general-purpose input or output, for the output compare b signal (ftob) of the free-running timer, or for irq 6 input. when used for ftob output, this pin is unaffected by the values in p6ddr and p6dr. when this pin is used for irq 6 input, p6 6 ddr should normally be cleared to 0, so that the value in p6dr will not generate interrupts. pin p6 7 : this pin can be used for general-purpose input or output, or irq 7 input. when it is used for irq 7 input, p6 7 ddr should normally be cleared to 0, so that the value in p6dr will not generate interrupts. reset and hardware standby mode: a reset or entry to the hardware standby mode clears p6ddr and p6dr to all 0 and makes all pins into input port pins. software standby mode: in the software standby mode, the free-running timer control registers are initialized but p6ddr and p6dr remain in their previous states. all pins become input or output port pins depending on the setting of p6ddr. output pins output the values in p6dr. rev. 3.0, 09/98, page 107 of 361 figures 6.6 (a) to 6.6 (d) shows schematic diagrams of port 6. p6 n rp6 reset internal data bus reset wp6 wp6d r r q q d d p6 n dr p6 n ddr c c wp6d: wp6: rp6: n = 0, 2 - 5 write port 6 ddr write port 6 read port 6 free-running timer module input capture input, counter clock input figure 6.6 (a) port 6 schematic diagram (pins p6 0 , p6 2 , p6 3 , p6 4 , and p6 5 ) rev. 3.0, 09/98, page 108 of 361 rp6 reset reset wp6 wp6d r r q q d d p6 1 dr p6 1 ddr c c wp6d: wp6: rp6: write port 6 ddr write port 6 read port 6 free-running timer module output enable output-compare output internal data bus p6 1 figure 6.6 (b) port 6 schematic diagram (pin p6 1 ) rev. 3.0, 09/98, page 109 of 361 rp6 reset reset internal data bus wp6 wp6d r r q q d d p6 6 dr p6 6 ddr c c wp6d: wp6: rp6: write port 6 ddr write port 6 read port 6 free-running timer module output enable output-compare output p6 6 irq6 enable register irq6 enable irq6 input figure 6.6 (c) port 6 schematic diagram (pin p6 6 ) rev. 3.0, 09/98, page 110 of 361 p6 7 rp6 reset reset internal data bus wp6 wp6d r r q q d d p6 7 dr p6 7 ddr c c wp6d: wp6: rp6: write port 6 ddr write port 6 read port 6 irq enable register irq7 enable irq7 input figure 6.6 (d) port 6 schematic diagram (pin p6 7 ) rev. 3.0, 09/98, page 111 of 361 6.8 port 7 port 7 is an 8-bit input port that also provides the analog input pins for the a/d converter module, and analog output pins for the d/a converter module. the pin functions are the same in both the expanded and single-chip modes. table 6.17 lists the pin functions. table 6.18 describes the port 7 data register, which simply consists of connections of the port 7 pins to the internal data bus. figure 6.7 (a) and 6.7 (b) show schematic diagrams of port 7. table 6.17 port 7 pin functions (modes 1 to 3) usage pin functions i/o port p7 0 p7 1 p7 2 p7 3 p7 4 p7 5 p7 6 p7 7 analog input an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 analog output ?????? da 0 da 1 table 6.18 port 7 register name abbreviation read/write initial value address port 7 data register p7dr r undetermined h'ffbe port 7 data register (p7dr) ? h'ffbe bit:76543210 p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 initial value: ******** read/write: r r r r r r r r note: depends on the levels of pins p7 7 to p7 0 . rev. 3.0, 09/98, page 112 of 361 p7n rp7: read port 7 n = 0 to 5 a/d converter module internal data bus analog input rp7 figure 6.7 (a) port 7 schematic diagram (pins p7 0 to p7 5 ) p7n rp7: read port 7 n = 6 or 7 a/d converter module analog output rp7 output enable analog input d/a converter module internal data bus figure 6.7 (b) port 7 schematic diagram (pins p7 6 and p7 7 ) rev. 3.0, 09/98, page 113 of 361 6.9 port 8 port 8 is a 7-bit input/output port that also provides pins for interrupt input and serial communication. table 6.19 lists the pin functions. table 6.19 port 8 pin functions pin i/o port serial communication interrupt input p8 0 input/output ?? p8 1 input/output ?? p8 2 input/output ?? p8 3 input/output ?? p8 4 input/output txd 1 output irq 3 input p8 5 input/output rxd 1 input irq 4 input p8 6 input/output sck 1 input/output irq 5 input pins of port 8 can drive a single ttl load and a 30pf capacitive load when they are used as output pins. they can also drive a darlington pair. table 6.20 details the port 8 registers. table 6.20 port 8 registers name abbreviation read/write initial value address port 8 data direction register p8ddr w h'80 h'ffbd port 8 data register p8dr r/w h'80 h'ffbf port 8 data direction register (p8ddr) ? h'ffbd bit:76543210 ? p8 6 ddr p8 5 ddr p8 4 ddr p8 3 ddr p8 2 ddr p8 1 ddr p8 0 ddr initial value: 1 0 0 0 0 0 0 0 read/write: ? wwwwwww p8ddr is an 8-bit register that selects the direction of each pin in port 8. a pin functions as an output pin if the corresponding bit in p8ddr is set to 1, and as in input pin if the bit is cleared to 0. bit 7 is reserved. it cannot be modified, and is always read as 1. rev. 3.0, 09/98, page 114 of 361 port 8 data register (p8dr) ? h'ffbf bit:76543210 ? p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 initial value: 1 0 0 0 0 0 0 0 read/write: ? r/w r/w r/w r/w r/w r/w r/w p8dr is an 8-bit register containing the data for pins p8 6 to p8 0 . when the cpu reads p8dr, for output pins (p8ddr = 1) it reads the value in the p8dr latch, but for input pins (p8ddr = 0), it obtains the logic level directly from the pin, bypassing the p8dr latch. this also applies to pins used for interrupt input and serial communication. bit 7 is reserved. it cannot be modified, and is always read as 1. pins 8 0 to p8 3 : these pins are available for general-purpose input or output. pin p8 4 : this pin has the same functions in all modes. it can be used for general-purpose input or output, for output of serial transmit data (txd 1 ), or for irq 3 input. when used for txd 1 output, this pin is unaffected by the values in p8ddr and p8dr. when this pin is used for irq 3 input, p8 4 ddr should normally be cleared to 0, so that the value in p8dr will not generate interrupts. pin p8 5 : this pin has the same functions in all modes. it can be used for general-purpose input or output, for input of serial receive data (rxd 1 ), or for irq 4 input. when used for rxd 1 input, this pin is unaffected by the values in p8ddr and p8dr. when this pin is used for irq 4 input, p8 5 ddr should normally be cleared to 0, so that the value in p8dr will not generate interrupts. pin p8 6 : this pin has the same functions in all modes. it can be used for general-purpose input or output, for serial clock input or output (sck 1 ), or for irq 5 input. when this pin is used for irq 5 input, p8 6 ddr should normally be cleared to 0, so that the value in p8dr will not generate interrupts. when used for sck 1 input or output, this pin is unaffected by the values in p8ddr and p8dr. reset: a reset clears bits p8 6 ddr to p8 0 ddr to 0 and clears the serial control bits and interrupt enable bits to 0, making p8 6 to p8 0 into input port pins. hardware standby mode: all pins are placed in the high-impedance state. software standby mode: in the software standby mode, the serial control register is initialized, but the interrupt enable register, p8ddr, and p8dr remain in their previous states. pins that were being used for serial communication revert to general-purpose input or output, depending on the value in p8ddr. other pins remain in their previous state. output pins output the values in p8dr. rev. 3.0, 09/98, page 115 of 361 figures 6.8 (a) to 6.8 (d) show schematic diagrams of port 8. p8 n rp8 reset internal data bus reset wp8 wp8d r r q q d d p8 n dr p8 n ddr c c wp8d: wp8: rp8: n = 0 to 3 write port 8 ddr write port 8 read port 8 figure 6.8 (a) port 8 schematic diagram (pins p8 0 to p8 3 ) rev. 3.0, 09/98, page 116 of 361 rp8 reset internal data bus reset wp8 wp8d r r q q d d p8 4 dr p8 4 ddr c c wp8d: wp8: rp8: write port 8 ddr write port 8 read port 8 transmit enable transmit data p8 4 irq enable register irq3 input irq3 enable sci module figure 6.8 (b) port 8 schematic diagram (pin p8 4 ) rev. 3.0, 09/98, page 117 of 361 rp8 reset wp8 r qd p8 5 dr c wp8d: wp8: rp8: write port 8 ddr write port 8 read port 8 sci module receive enable internal data bus p8 5 irq enable register irq4 enable receive data irq4 input reset wp8d r qd p8 5 ddr c figure 6.8 (c) port 8 schematic diagram (pin p8 5 ) rev. 3.0, 09/98, page 118 of 361 rp8 reset reset wp8 wp8d r r q q d d p8 6 dr p8 6 ddr c c wp8d: wp8: rp8: write port 8 ddr write port 8 read port 8 sci module clock input enable internal data bus p8 6 irq enable register irq5 enable irq5 input clock input clock output enable clock output figure 6.8 (d) port 8 schematic diagram (pin p8 6 ) rev. 3.0, 09/98, page 119 of 361 6.10 port 9 port 9 is an 8-bit input/output port that also provides pins for interrupt input ( irq 0 to irq 2 ), a/d trigger input, system clock ( f ) output, and bus control signals (in the expanded modes). pins p9 7 to p9 3 have different functions in different modes. pins p9 2 to p9 0 have the same functions in all modes. table 6.21 lists the pin functions. table 6.21 port 9 pin functions pin expanded modes single-chip mode p9 0 p9 0 input/output , irq 2 input, and adtrg input (simultaneously) p9 1 p9 1 input/output and irq 1 input (simultaneously) p9 2 p9 2 input/output and irq 0 input (simultaneously) p9 3 rd output p9 3 input/output p9 4 wr output p9 4 input/output p9 5 as output p9 5 input/output p9 6 f output p9 6 input or f output p9 7 wait input p9 7 input/output pins of port 9 can drive a single ttl load and a 90pf capacitive load when they are used as output pins. table 6.22 details the port 9 registers. table 6.22 port 9 registers name abbreviation read/write initial value address port 9 data direction register p9ddr w h'40 (modes 1 and 2) h'00 (mode 3) h'ffc0 port 9 data register p9dr r/w * 1 undetermined * 2 h'ffc1 notes: 1. bit 6 is read-only. 2. bit 6 is undetermined. other bits are initially 0. rev. 3.0, 09/98, page 120 of 361 port 9 data direction register (p9ddr) ? h'ffc0 bit 76543210 p9 7 ddr p9 6 ddr p9 5 ddr p9 4 ddr p9 3 ddr p9 2 ddr p9 1 ddr p9 0 ddr modes 1 and 2 initial value 0 1 0 0 0 0 0 0 read/write w ? wwwwww mode 3 initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w p9ddr is an 8-bit register that selects the direction of each pin in port 9. a pin functions as an output pin if the corresponding bit in p9ddr is set to 1, and as in input pin if the bit is cleared to 0. port 9 data register (p9dr) ? h'ffc1 bit:76543210 p9 7 p9 6 p9 5 p9 4 p9 3 p9 2 p9 1 p9 0 initial value: 0 * 000000 read/write: r/w r r/w r/w r/w r/w r/w r/w note: determined by the level at pin p9 6 . p9dr is an 8-bit register containing the data for pins p9 7 to p9 0 . when the cpu reads p9dr, for output pins (p9ddr = 1) it reads the value in the p9dr latch, but for input pins (p9ddr = 0), it obtains the logic level directly from the pin, bypassing the p9dr latch. this also applies to pins used for interrupt input, a/d trigger input, clock output, and control signal input or output. pins p9 0 , p9 1 , and p9 2 : can be used for general-purpose input or output, interrupt request input, or a/d trigger input. see table 6.21. if a pin is used for interrupt or a/d trigger input, its data direction bit should be cleared to 0, so that the output from p9dr will not generate an interrupt request or a/d trigger signal. pins p9 3 , p9 4 , and p9 5 : in modes 1 and 2 (the expanded modes), these pins are used for output of the rd , wr , and as bus control signals. they are unaffected by the values in p9ddr and p9dr. in mode 3 (single-chip mode), these pins can be used for general-purpose input or output. pin p9 6 : in modes 1 and 2, this pin is used for system clock ( f ) output. rev. 3.0, 09/98, page 121 of 361 in mode 3, this pin is used for general-purpose input if p96ddr is cleared to 0, or system clock output if p9 6 ddr is set to 1. pin p9 7 : in modes 1 and 2, this pin is used for input of the wait bus control signal. it is unaffected by the values in p9ddr and p9dr. in mode 3 (single-chip mode), this pin can be used for general-purpose input or output. reset: in the single-chip mode (mode 3), a reset initializes all pins of port 9 to the general- purpose input function. in the expanded modes (modes 1 and 2), p9 0 to p9 2 are initialized as input port pins, and p9 3 to p9 7 are initialized to their bus control and system clock output functions. hardware standby mode: all pins are placed in the high-impedance state. software standby mode: all pins remain in their previous state. for rd , wr , as , and f this means the high output state. rev. 3.0, 09/98, page 122 of 361 figures 6.9 (a) to 6.9 (e) show schematic diagrams of port 9. p9 0 rp9 reset internal data bus reset wp9 wp9d r r q q d d p9 0 dr p9 0 ddr c c wp9d: wp9: rp9: write port 9 ddr write port 9 read port 9 irq enable register irq2 enable a/d converter module adtrg irq2 input figure 6.9 (a) port 9 schematic diagram (pin p9 0 ) rev. 3.0, 09/98, page 123 of 361 p9 n rp9 reset reset wp9 wp9d r r q q d d p9 n dr p9 n ddr c c wp9d: wp9: rp9: n = 1, 2 write port 9 ddr write port 9 read port 9 irq0 input irq1 input irq enable register irq0 enable irq1 enable internal data bus figure 6.9 (b) port 9 schematic diagram (pins p9 1 and p9 2 ) rev. 3.0, 09/98, page 124 of 361 rp9 reset reset wp9 wp9d r r q q d d p9 n dr p9 n ddr c c wp9d: wp9: rp9: n = 3, 4, 5 write port 9 ddr write port 9 read port 9 rd output wr output as ouput p9 n hardware standby mode 1 or 2 mode 3 mode 1 or 2 internal data bus figure 6.9 (c) port 9 schematic diagram (pins p9 3 , p9 4 , and p9 5 ) rev. 3.0, 09/98, page 125 of 361 p96 rp9 reset internal data bus mode 1, 2 wp9d r s qd p9 6ddr c wp9d: wp9: rp9: note: * set-priority write port 9 ddr write port 9 read port 9 hardware standby * ? figure 6.9 (d) port 9 schematic diagram (pin p9 6 ) rev. 3.0, 09/98, page 126 of 361 p9 7 rp9 reset reset internal data bus wp9 wp9d r r q q d d p9 7 dr p9 7ddr c c wp9d: wp9: rp9: write port 9 ddr write port 9 read port 9 mode 1 or 2 wait input figure 6.9 (e) port 9 schematic diagram (pin p9 7 ) rev. 3.0, 09/98, page 127 of 361 section 7 16-bit free-running timer 7.1 overview the h8/338 series has an on-chip 16-bit free-running timer (frt) module that uses a 16-bit free- running counter as a time base. applications of the frt module include rectangular-wave output (up to two independent waveforms), input pulse width measurement, and measurement of external clock periods. 7.1.1 features the features of the free-running timer module are listed below. selection of four clock sources the free-running counter can be driven by an internal clock source ( f /2, f /8, or f /32), or an external clock input (enabling use as an external event counter). two independent comparators each comparator can generate an independent waveform. four input capture channels the current count can be captured on the rising or falling edge (selectable) of an input signal. the four input capture registers can be used separately, or in a buffer mode. counter can be cleared under program control the free-running counters can be cleared on compare-match a. seven independent interrupts compare-match a and b, input capture a to d, and overflow interrupts are requested independently. 7.1.2 block diagram figure 7.1 shows a block diagram of the free-running timer. rev. 3.0, 09/98, page 128 of 361 external clock source ftoa ftob ftia ftib ftic ftid internal clock sources ?/2 ?/8 ?/32 ftci clock overflow clear compare- match b control logic capture clock select cora (h/l) tcsr tier comparator a frc (h/l) comparator b module data bus bus interface ocrb (h/l) icra (h/l) icrb (h/l) icrc (h/l) icrd (h/l) tcr tocr internal data bus icia icib icic icid ocia ocib fovi interrupt signals ocra, b frc icra to d tcsr tier tcr tocr legend: free-running counter (16 bits) output compare register a, b (16 bits) input capture register a, b, c, d (16 bits) timer control/status register (8 bits) timer interrupt enable register (8 bits) timer control register (8 bits) timer output compare control compare-match a figure 7.1 block diagram of 16-bit free-running timer rev. 3.0, 09/98, page 129 of 361 7.1.3 input and output pins table 7.1 lists the input and output pins of the free-running timer module. table 7.1 input and output pins of free-running timer module name abbreviation i/o function counter clock input ftci input input of external free-running counter clock signal output compare a ftoa output output controlled by comparator a output compare b ftob output output controlled by comparator b input capture a ftia input trigger for capturing current count into input capture register a input capture b ftib input trigger for capturing current count into input capture register b input capture c ftic input trigger for capturing current count into input capture register c input capture d ftid input trigger for capturing current count into input capture register d 7.1.4 register configuration table 7.2 lists the registers of the free-running timer module. table 7.2 register configuration name abbreviation r/w initial value address timer interrupt enable register tier r/w h'01 h'ff90 timer control/status register tcsr r/(w) * 1 h'00 h'ff91 free-running counter (high) frc (h) r/w h'00 h'ff92 free-running counter (low) frc (l) r/w h'00 h'ff93 output compare register a/b (high) * 2 ocra/b (h) r/w h'ff h'ff94 * 2 output compare register a/b (low) * 2 ocra/b (l) r/w h'ff h'ff95 * 2 timer control register tcr r/w h'00 h'ff96 timer output compare control register tocr r/w h'e0 h'ff97 input capture register a (high) icra (h) r h'00 h'ff98 input capture register a (low) icra (l) r h'00 h'ff99 notes: 1. software can write a 0 to clear bits 7 to 1, but cannot write a 1 in these bits. 2. ocra and ocrb share the same addresses. access is controlled by the ocrs bit in tocr. rev. 3.0, 09/98, page 130 of 361 table 7.2 register configuration (cont) name abbreviation r/w initial value address input capture register b (high) icrb (h) r h'00 h'ff9a input capture register b (low) icrb (l) r h'00 h'ff9b input capture register c (high) icrc (h) r h'00 h'ff9c input capture register c (low) icrc (l) r h'00 h'ff9d input capture register d (high) icrd (h) r h'00 h'ff9e input capture register d (low) icrd (l) r h'00 h'ff9f 7.2 register descriptions 7.2.1 free-running counter (frc) ? h'ff92 bit:1514131211109876543210 initial value:0000000000000000 read/write: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w the frc is a 16-bit readable/writable up-counter that increments on an internal pulse generated from a clock source. the clock source is selected by the clock select 1 and 0 bits (cks1 and cks0) of the timer control register (tcr). when the frc overflows from h'ffff to h'0000, the overflow flag (ovf) in the timer control/status register (tcsr) is set to 1. because the frc is a 16-bit register, a temporary register (temp) is used when the frc is written or read. see section 7.3, cpu interface, for details. the frc is initialized to h'0000 at a reset and in the standby modes. it can also be cleared by compare-match a. rev. 3.0, 09/98, page 131 of 361 7.2.2 output compare registers a and b (ocra and ocrb) ? h'ff94 bit:1514131211109876543210 initial value:1111111111111111 read/write: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ocra and ocrb are 16-bit readable/writable registers, the contents of which are continually compared with the value in the frc. when a match is detected, the corresponding output compare flag (ocfa or ocfb) is set in the timer control/status register (tcsr). in addition, if the output enable bit (oea or oeb) in the timer output compare control register (tocr) is set to 1, when the output compare register and frc values match, the logic level selected by the output level bit (olvla or olvlb) in the tocr is output at the output compare pin (ftoa or ftob). ocra and ocrb share the same address. they are differentiated by the ocrs bit in the tocr. a temporary register (temp) is used for write access, as explained in section 7.3, cpu interface. ocra and ocrb are initialized to h'ffff at a reset and in the standby modes. 7.2.3 input capture registers a to d (icra to icrd) ? h'ff98, h'ff9a, h'ff9c, h'ff9e bit:1514131211109876543210 initial value:0000000000000000 read/write: r rrrrrrrrrrrrrrr each input capture register is a 16-bit read-only register. when the rising or falling edge of the signal at an input capture pin (ftia to ftid) is detected, the current value of the frc is copied to the corresponding input capture register (icra to icrd).* at the same time, the corresponding input capture flag (icfa to icfd) in the timer control/status register (tcsr) is set to 1. the input capture edge is selected by the input edge select bits (iedga to iedgd) in the timer control register (tcr). note: the frc contents are transferred to the input capture register regardless of the value of the input capture flag (icfa/b/c/d). rev. 3.0, 09/98, page 132 of 361 input capture can be buffered by using the input capture registers in pairs. when the bufea bit in the timer control register (tcr) is set to 1, icrc is used as a buffer register for icra as shown in figure 7.2. when an ftia input is received, the old icra contents are moved into icrc, and the new frc count is copied into icra. ftia bufea iedga iedgc icrc icra frc edge detect and capture signal generating circuit bufea iedga iedgc icrc icra frc : buffer enable a : edge select a : input edge select c : input capture register c : input capture register a : free-running counter figure 7.2 input capture buffering similarly, when the bufeb bit in tier is set to 1, icrd is used as a buffer register for icrb. when input capture is buffered, if the two input edge bits are set to different values (iedga 1 iedgc or iedgb 1 iedgd), then input capture is triggered on both the rising and falling edges of the ftia or ftib input signal. if the two input edge bits are set to the same value (iedga = iedgc or iedgb = iedgd), then input capture is triggered on only one edge. rev. 3.0, 09/98, page 133 of 361 table 7.3 buffered input capture edge selection (example) iedga iedgc input capture edge 0 0 captured on falling edge of input capture a (ftia) (initial value) 0 1 captured on both rising and falling edges of input capture a (ftia) 10 1 1 captured on rising edge of input capture a (ftia) because the input capture registers are 16-bit registers, a temporary register (temp) is used when they are read. see section 7.3, cpu interface, for details. to ensure input capture, the width of the input capture pulse (ftia, ftib, ftic, ftid) should be at least 1.5 system clock periods (1.5 f ). when triggering is enabled on both edges, the input capture pulse width should be at least 2.5 system clock periods. the input capture registers are initialized to h'0000 at a reset and in the standby modes. note: when input capture is detected, the frc value is transferred to the input capture register even if the input capture flag is already set. rev. 3.0, 09/98, page 134 of 361 7.2.4 timer interrupt enable register (tier)-h'ff90 bit:76543210 iciae icibe icice icide ociae ocibe ovie ? initial value: 0 0 0 0 0 0 0 1 read/write: r/w r/w r/w r/w r/w r/w r/w ? the tier is an 8-bit readable/writable register that enables and disables interrupts. the tier is initialized to h'01 (all interrupts disabled) at a reset and in the standby modes. bit 7 ? input capture interrupt a enable (iciae): this bit selects whether to request input capture interrupt a (icia) when input capture flag a (icfa) in the timer status/control register (tcsr) is set to 1. bit 7 iciae description 0 input capture interrupt request a (icia) is disabled. (initial value) 1 input capture interrupt request a (icia) is enabled. bit 6 ? input capture interrupt b enable (icibe): this bit selects whether to request input capture interrupt b (icib) when input capture flag b (icfb) in the timer status/control register (tcsr) is set to 1. bit 6 icibe description 0 input capture interrupt request b (icib) is disabled. (initial value) 1 input capture interrupt request b (icib) is enabled. bit 5 ? input capture interrupt c enable (icice): this bit selects whether to request input capture interrupt c (icic) when input capture flag c (icfc) in the timer status/control register (tcsr) is set to 1. bit 5 icice description 0 input capture interrupt request c (icic) is disabled. (initial value) 1 input capture interrupt request c (icic) is enabled. rev. 3.0, 09/98, page 135 of 361 bit 4 ? input capture interrupt d enable (icide): this bit selects whether to request input capture interrupt d (icid) when input capture flag d (icfd) in the timer status/control register (tcsr) is set to 1. bit 4 icide description 0 input capture interrupt request d (icid) is disabled. (initial value) 1 input capture interrupt request d (icid) is enabled. bit 3 ? output compare interrupt a enable (ociae): this bit selects whether to request output compare interrupt a (ocia) when output compare flag a (ocfa) in the timer status/control register (tcsr) is set to 1. bit 3 ociae description 0 output compare interrupt request a (ocia) is disabled. (initial value) 1 output compare interrupt request a (ocia) is enabled. bit 2 ? output compare interrupt b enable (ocibe): this bit selects whether to request output compare interrupt b (ocib) when output compare flag b (ocfb) in the timer status/control register (tcsr) is set to 1. bit 2 ocibe description 0 output compare interrupt request b (ocib) is disabled. (initial value) 1 output compare interrupt request b (ocib) is enabled. bit 1 ? timer overflow interrupt enable (ovie): this bit selects whether to request a free- running timer overflow interrupt (fovi) when the timer overflow flag (ovf) in the timer status/control register (tcsr) is set to 1. bit 1 ovie description 0 timer overflow interrupt request (fovi) is disabled. (initial value) 1 timer overflow interrupt request (fovi) is enabled. bit 0 ? reserved: this bit cannot be modified and is always read as 1. rev. 3.0, 09/98, page 136 of 361 7.2.5 timer control/status register (tcsr) ? h'ff91 bit:76543210 icfa icfb icfc icfd ocfa ocfb ovf cclra initial value: 0 0 0 0 0 0 0 0 read/write: r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/w the tcsr is an 8-bit readable and partially writable* register that contains the seven interrupt flags and specifies whether to clear the counter on compare-match a (when the frc and ocra values match). note: software can write a 0 in bits 7 to 1 to clear the flags, but cannot write a 1 in these bits. the tcsr is initialized to h'00 at a reset and in the standby modes. bit 7 ? input capture flag a (icfa): this status bit is set to 1 to flag an input capture a event. if bufea = 0, icfa indicates that the frc value has been copied to icra. if bufea = 1, icfa indicates that the old icra value has been moved into icrc and the new frc value has been copied to icra. icfa must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 7 icfa description 0 to clear icfa, the cpu must read icfa after it has been set to 1, (initial value) then write a 0 in this bit. 1 this bit is set to 1 when an ftia input signal causes the frc value to be copied to icra. rev. 3.0, 09/98, page 137 of 361 bit 6 ? input capture flag b (icfb): this status bit is set to 1 to flag an input capture b event. if bufeb = 0, icfb indicates that the frc value has been copied to icrb. if bufeb = 1, icfb indicates that the old icrb value has been moved into icrd and the new frc value has been copied to icrb. icfb must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 6 icfb description 0 to clear icfb, the cpu must read icfb after it has been set to 1, (initial value) then write a 0 in this bit. 1 this bit is set to 1 when an ftib input signal causes the frc value to be copied to icrb. bit 5 ? input capture flag c (icfc): this status bit is set to 1 to flag input of a rising or falling edge of ftic as selected by the iedgc bit. when bufea = 0, this indicates capture of the frc count in icrc. when bufea = 1, however, the frc count is not captured, so icfc becomes simply an external interrupt flag. in other words, the buffer mode frees ftic for use as a general-purpose interrupt signal (which can be enabled or disabled by the icice bit). icfc must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 5 icfc description 0 to clear icfc, the cpu must read icfc after it has been set to 1, (initial value) then write a 0 in this bit. 1 this bit is set to 1 when an ftic input signal is received. bit 4 ? input capture flag d (icfd): this status bit is set to 1 to flag input of a rising or falling edge of ftid as selected by the iedgd bit. when bufeb = 0, this indicates capture of the frc count in icrd. when bufeb = 1, however, the frc count is not captured, so icfd becomes simply an external interrupt flag. in other words, the buffer mode frees ftid for use as a general-purpose interrupt signal (which can be enabled or disabled by the icide bit). icfd must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 4 icfd description 0 to clear icfd, the cpu must read icfd after it has been set to 1, (initial value) then write a 0 in this bit. 1 this bit is set to 1 when an ftid input signal is received. rev. 3.0, 09/98, page 138 of 361 bit 3 ? output compare flag a (ocfa): this status flag is set to 1 when the frc value matches the ocra value. this flag must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 3 ocfa description 0 to clear ocfa, the cpu must read ocfa after it has been set to 1, (initial value) then write a 0 in this bit. 1 this bit is set to 1 when frc = ocra. bit 2 ? output compare flag b (ocfb): this status flag is set to 1 when the frc value matches the ocrb value. this flag must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 2 ocfb description 0 to clear ocfb, the cpu must read ocfb after it has been set to 1, (initial value) then write a 0 in this bit. 1 this bit is set to 1 when frc = ocrb. bit 1 ? timer overflow flag (ovf): this status flag is set to 1 when the frc overflows (changes from h'ffff to h'0000). this flag must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 1 ovf description 0 to clear ovf, the cpu must read ovf after it has been set to 1, (initial value) then write a 0 in this bit. 1 this bit is set to 1 when frc changes from h'ffff to h'0000. bit 0 ? counter clear a (cclra): this bit selects whether to clear the frc at compare-match a (when the frc and ocra values match). bit 0 cclra description 0 the frc is not cleared. (initial value) 1 the frc is cleared at compare-match a. rev. 3.0, 09/98, page 139 of 361 7.2.6 timer control register (tcr)-h'ff96 bit:76543210 iedga iedgb iedgc iedgd bufea bufeb cks1 cks0 initial value: 0 0 0 0 0 0 0 0 read/write: r/w r/w r/w r/w r/w r/w r/w r/w the tcr is an 8-bit readable/writable register that selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the frc clock source. the tcr is initialized to h'00 at a reset and in the standby modes. bit 7 ? input edge select a (iedga): this bit causes input capture a events to be recognized on the selected edge of the input capture a signal (ftia). bit 7 iedga description 0 input capture a events are recognized on the falling edge of ftia. (initial value) 1 input capture a events are recognized on the rising edge of ftia. bit 6 ? input edge select b (iedgb): this bit causes input capture b events to be recognized on the selected edge of the input capture b signal (ftib). bit 6 iedgb description 0 input capture b events are recognized on the falling edge of ftib. (initial value) 1 input capture b events are recognized on the rising edge of ftib. bit 5 ? input edge select c (iedgc): this bit causes input capture c events to be recognized on the selected edge of the input capture c signal (ftic). bit 5 iedgc description 0 input capture c events are recognized on the falling edge of ftic. (initial value) 1 input capture c events are recognized on the rising edge of ftic. rev. 3.0, 09/98, page 140 of 361 bit 4 ? input edge select d (iedgd): this bit causes input capture d events to be recognized on the selected edge of the input capture d signal (ftid). bit 4 iedgd description 0 input capture d events are recognized on the falling edge of ftid. (initial value) 1 input capture d events are recognized on the rising edge of ftid. bit 3 ? buffer enable a (bufea): this bit selects whether to use icrc as a buffer register for icra. bit 3 bufea description 0 icrc is used for input capture c. (initial value) 1 icrc is used as a buffer register for input capture a. input c is not captured. bit 2 ? buffer enable b (bufeb): this bit selects whether to use icrd as a buffer register for icrb. bit 2 bufeb description 0 icrd is used for input capture d. (initial value) 1 icrd is used as a buffer register for input capture b. input d is not captured. bits 1 and 0 ? clock select (cks1 and cks0): these bits select external clock input or one of three internal clock sources for the frc. external clock pulses are counted on the rising edge. bit 1 cks1 bit 0 cks0 description 00 f /2 internal clock source (initial value) 01 f /8 internal clock source 10 f /32 internal clock source 1 1 external clock source (rising edge) rev. 3.0, 09/98, page 141 of 361 7.2.7 timer output compare control register (tocr) ? h'ff97 bit:76543210 ??? ocrs oea oeb olvla olvlb initial value: 1 1 1 0 0 0 0 0 read/write: ??? r/w r/w r/w r/w r/w the tocr is an 8-bit readable/writable register that controls the output compare function. the tocr is initialized to h'e0 at a reset and in the standby modes. bits 7 to 5 ? reserved: these bits cannot be modified and are always read as 1. bit 4 ? output compare register select (ocrs): when the cpu accesses addresses h'ff94 and h'ff95, this bit directs the access to either ocra or ocrb. these two registers share the same addresses as follows: upper byte of ocra and upper byte of ocrb: h'ff94 lower byte of ocra and lower byte of ocrb: h'ff95 bit 4 ocrs description 0 the cpu can access ocra. (initial value) 1 the cpu can access ocrb. bit 3 ? output enable a (oea): this bit enables or disables output of the output compare a signal (ftoa). bit 3 oea description 0 output compare a output is disabled. (initial value) 1 output compare a output is enabled. bit 2 ? output enable b (oeb): this bit enables or disables output of the output compare b signal (ftob). bit 2 oeb description 0 output compare b output is disabled. (initial value) 1 output compare b output is enabled. rev. 3.0, 09/98, page 142 of 361 bit 1 ? output level a (olvla): this bit selects the logic level to be output at the ftoa pin when the frc and ocra values match. bit 1 olvla description 0 a 0 logic level (low) is output for compare-match a. (initial value) 1 a 1 logic level (high) is output for compare-match a. bit 0 ? output level b (olvlb): this bit selects the logic level to be output at the ftob pin when the frc and ocrb values match. bit 0 olvlb description 0 a 0 logic level (low) is output for compare-match b. (initial value) 1 a 1 logic level (high) is output for compare-match b. rev. 3.0, 09/98, page 143 of 361 7.3 cpu interface the free-running counter (frc), output compare registers (ocra and ocrb), and input capture registers (icra to icrd) are 16-bit registers, but they are connected to an 8-bit data bus. when the cpu accesses these registers, to ensure that both bytes are written or read simultaneously, the access is performed using an 8-bit temporary register (temp). these registers are written and read as follows: register write when the cpu writes to the upper byte, the byte of write data is placed in temp. next, when the cpu writes to the lower byte, this byte of data is combined with the byte in temp and all 16 bits are written in the register simultaneously. register read when the cpu reads the upper byte, the upper byte of data is sent to the cpu and the lower byte is placed in temp. when the cpu reads the lower byte, it receives the value in temp. (as an exception, when the cpu reads ocra or ocrb, it reads both the upper and lower bytes directly, without using temp.) programs that access these registers should normally use word access. equivalently, they may access first the upper byte, then the lower byte by two consecutive byte accesses. data will not be transferred correctly if the bytes are accessed in reverse order, or if only one byte is accessed. coding examples to write the contents of general register r0 to ocra: mov.w r0, @ocra to transfer the contents of icra to general register r0: mov.w @icra, r0 figure 7.3 shows the data flow when the frc is accessed. the other registers are accessed in the same way. rev. 3.0, 09/98, page 144 of 361 (1) upper byte write bus interface cpu writes data h'aa temp [h'aa] frc h [ ] frc l [ ] module data bus (2) lower byte write bus interface cpu writes data h'55 temp [h'aa] frc h [h'aa] frc l [h'55] module data bus figure 7.3 (a) write access to frc (when cpu writes h'aa55) rev. 3.0, 09/98, page 145 of 361 (1) upper byte read bus interface bus interface cpu reads data h'aa temp [h'55] frc h [h'aa] frc l [h'55] module data bus (2) lower byte read cpu reads data h'55 temp [h'55] frc h [ ] frc l [ ] module data bus figure 7.3 (b) read access to frc (when frc contains h'aa55) rev. 3.0, 09/98, page 146 of 361 7.4 operation 7.4.1 frc incrementation timing the frc increments on a pulse generated once for each period of the selected (internal or external) clock source. the clock source is selected by bits cks0 and cks1 in the tcr. internal clock: the internal clock sources ( f /2, f /8, f /32) are created from the system clock ( f ) by a prescaler. the frc increments on a pulse generated from the falling edge of the prescaler output. see figure 7.4. n n - 1 n + 1 internal clock ? frc clock pulse frc figure 7.4 increment timing for internal clock source external clock: if external clock input is selected, the frc increments on the rising edge of the ftci clock signal. figure 7.5 shows the increment timing. the pulse width of the external clock signal must be at least 1.5 system clock ( f ) periods. the counter will not increment correctly if the pulse width is shorter than 1.5 system clock periods. rev. 3.0, 09/98, page 147 of 361 n n + 1 ftci frc clock pulse frc ? figure 7.5 increment timing for external clock source n n n n n + 1 n + 1 frc ocra ? internal compare- match a signal olvla ftoa clear* note: * cleared by software figure 7.6 minimum external clock pulse width rev. 3.0, 09/98, page 148 of 361 7.4.2 output compare timing (1) setting of output compare flags a and b (ocfa and ocfb): the output compare flags are set to 1 by an internal compare-match signal generated when the frc value matches the ocra or ocrb value. this compare-match signal is generated at the last state in which the two values match, just before the frc increments to a new value. accordingly, when the frc and ocr values match, the compare-match signal is not generated until the next period of the clock source. figure 7.7 shows the timing of the setting of the output compare flags. h' 0000 n internal compare- match a signal ? frc figure 7.7 setting of output compare flags (2) output timing: when a compare-match occurs, the logic level selected by the output level bit (olvla or olvlb) in tocr is output at the output compare pin (ftoa or ftob). figure 7.8 shows the timing of this operation for compare-match a. ? internal input capture signal input at fti pin figure 7.8 timing of output compare a rev. 3.0, 09/98, page 149 of 361 (3) frc clear timing: if the cclra bit in the tcsr is set to 1, the frc is cleared when compare-match a occurs. figure 7.9 shows the timing of this operation. ? internal input capture signal input at fti pin read cycle: cpu reads upper byte of icr t 1 t 2 t 3 figure 7.9 clearing of frc by compare-match a 7.4.3 input capture timing (1) input capture timing: an internal input capture signal is generated from the rising or falling edge of the signal at the input capture pin ftix (x = a, b, c, d), as selected by the corresponding iedgx bit in tcr. figure 7.10 shows the usual input capture timing when the rising edge is selected (iedgx = 1). n n n + 1 n + 1 n n m n m m m n ftia ? internal input capture signal icra frc icrc figure 7.10 input capture timing (usual case) rev. 3.0, 09/98, page 150 of 361 if the upper byte of icra/b/c/d is being read when the corresponding input capture signal arrives, the internal input capture signal is delayed by one state. figure 7.11 shows the timing for this case. ? input at ftia pin internal input capture signal t 1 t 2 t 3 read cycle: cpu reads upper byte of icra or icrc figure 7.11 input capture timing (1-state delay) in buffer mode, this delay occurs if the cpu is reading either of the two registers concerned. when icra and icrc are used in buffer mode, for example, if the upper byte of either icra or icrc is being read when the ftia input arrives, the internal input capture signal is delayed by one state. figure 7.12 shows the timing for this case. the case of icrb and icrd is similar. frc icfa to d icra to d ? internal input capture signal n n figure 7.12 input capture timing (1-state delay, buffer mode) rev. 3.0, 09/98, page 151 of 361 figure 7.13 shows how input capture operates when icra and icrc are used in buffer mode and iedga and iedgc are set to different values (iedga = 0 and iedgc = 1, or iedga = 1 and iedgc = 0), so that input capture is performed on both the rising and falling edges of ftia. n n n + 1 frc ? ocra or b internal compare- match signal ocfa or b figure 7.13 buffered input capture with both edges selected in this mode, input capture does not cause the frc contents to be copied to icrc. however, input capture flag c still sets on the input capture edge selected by iedgc, and if the interrupt enable bit (icice) is set, a cpu interrupt is requested. the situation when icrb and icrd are used in buffer mode is similar. (2) timing of input capture flag (icf) setting: the input capture flag icfx (x = a, b, c, d) is set to 1 by the internal input capture signal. figure 7.14 shows the timing of this operation. h' 0000 n internal compare- match a signal ? frc figure 7.14 setting of input capture flag rev. 3.0, 09/98, page 152 of 361 7.4.4 setting of frc overflow flag (ovf) the frc overflow flag (ovf) is set to 1 when the frc overflows (changes from h'ffff to h'0000). figure 7.15 shows the timing of this operation. frc h'ffff ocra ocrb h'0000 ftoa ftob clear counter 6 figure 7.15 setting of overflow flag (ovf) 7.5 interrupts the free-running timer can request seven types of interrupts: input capture a to d (icia, icib, icic, icid), output compare a and b (ocia and ocib), and overflow (fovi). each interrupt is requested when the corresponding enable and flag bits are set. independent signals are sent to the interrupt controller for each type of interrupt. table 7.4 lists information about these interrupts. table 7.4 free-running timer interrupts interrupt description priority icia requested when icfa and iciae are set high icib requested when icfb and icibe are set icic requested when icfc and icice are set icid requested when icfd and icide are set ocia requested when ocfa and ociae are set ocib requested when ocfb and ocibe are set fovi requested when ovf and ovie are set low rev. 3.0, 09/98, page 153 of 361 7.6 sample application in the example below, the free-running timer is used to generate two square-wave outputs with a 50% duty cycle and arbitrary phase relationship. the programming is as follows: (1) the cclra bit in the tcsr is set to 1. (2) each time a compare-match interrupt occurs, software inverts the corresponding output level bit in tocr (olvla or olvlb). ? internal address bus internal write signal frc clear signal frc write cycle: cpu write to lower byte of frc t 1 t 2 t 3 h' 0000 n frc address figure 7.16 square-wave output (example) rev. 3.0, 09/98, page 154 of 361 7.7 application notes application programmers should note that the following types of contention can occur in the free- running timers. (1) contention between frc write and clear: if an internal counter clear signal is generated during the t 3 state of a write cycle to the lower byte of the free-running counter, the clear signal takes priority and the write is not performed. figure 7.17 shows this type of contention. ? internal address bus internal write signal frc clock pulse frc write cycle: cpu write to lower byte of frc t 1 t 2 t 3 write data nm frc address figure 7.17 frc write-clear contention (2) contention between frc write and increment: if an frc increment pulse is generated during the t 3 state of a write cycle to the lower byte of the free-running counter, the write takes priority and the frc is not incremented. rev. 3.0, 09/98, page 155 of 361 figure 7.18 shows this type of contention. ? internal address bus internal write signal frc ocra or ocrb compare-match a or b signal write cycle: cpu write to lower byte of ocra or ocrb t 1 t 2 t 3 n + 1 n m inhibited n ocr address write data figure 7.18 frc write-increment contention (3) contention between ocr write and compare-match: if a compare-match occurs during the t 3 state of a write cycle to the lower byte of ocra or ocrb, the write takes priority and the compare-match signal is inhibited. rev. 3.0, 09/98, page 156 of 361 (4) incrementation caused by changing of internal clock source: when an internal clock source is changed, the changeover may cause the frc to increment. this depends on the time at which the clock select bits (cks1 and cks0) are rewritten, as shown in table 7.5. the pulse that increments the frc is generated at the falling edge of the internal clock source. if clock sources are changed when the old source is high and the new source is low, as in case no. 3 in table 7.5, the changeover generates a falling edge that triggers the frc increment clock pulse. switching between an internal and external clock source can also cause the frc to increment. table 7.5 effect of changing internal clock sources no. description timing chart 1 low ? low: cks1 and cks0 are rewritten while both clock sources are low. old clock source new clock source frc clock pulse frc cks rewrite n n + 1 2 low ? high: cks1 and cks0 are rewritten while old clock source is low and new clock source is high. old clock source new clock source frc clock pulse frc cks rewrite n n + 1 n + 2 rev. 3.0, 09/98, page 157 of 361 table 7.5 effect of changing internal clock sources (cont) no. description timing chart 3 high ? low: cks1 and cks0 are rewritten while old clock source is high and new clock source is low. old clock source new clock source frc clock pulse frc n n + 1 n + 2 cks rewrite * 4 high ? high: cks1 and cks0 are rewritten while both clock sources are high. old clock source new clock source frc clock pulse frc n n + 1 cks rewrite n + 2 note: the switching of clock sources is regarded as a falling edge that increments the frc. rev. 3.0, 09/98, page 158 of 361 rev. 3.0, 09/98, page 159 of 361 section 8 8-bit timers 8.1 overview the h8/338 series includes an 8-bit timer module with two channels (tmr0 and tmr1). each channel has an 8-bit counter (tcnt) and two time constant registers (tcora and tcorb) that are constantly compared with the tcnt value to detect compare-match events. one application of the 8-bit timer module is to generate a rectangular-wave output with an arbitrary duty cycle. 8.1.1 features the features of the 8-bit timer module are listed below. selection of seven clock sources the counters can be driven by one of six internal clock signals or an external clock input (enabling use as an external event counter). selection of three ways to clear the counters the counters can be cleared on compare-match a or b, or by an external reset signal. timer output controlled by two time constants the timer output signal in each channel is controlled by two independent time constants, enabling the timer to generate output waveforms with an arbitrary duty factor. three independent interrupts compare-match a and b and overflow interrupts can be requested independently. rev. 3.0, 09/98, page 160 of 361 8.1.2 block diagram figure 8.1 shows a block diagram of one channel in the 8-bit timer module. the other channel is identical. external clock source tmci tmo tmri internal clock sources channel 0 channel 1 ?/2 ?/8 ?/32 ?/64 ?/256 ?/1024 ?/2 ?/8 ?/64 ?/128 ?/1024 ?/2048 clock overflow clear compare-match b clock select tcora comparator a tcnt comparator b module data bus bus interface tcorb tcsr tcr internal data bus cmia cmib ovi interrupt signals tcr tcsr tcora tcorb tcnt : timer control register (8 bits) : timer control status register (8 bits) : time constant register a (8 bits) : time constant register b (8 bits) : timer counter compare-match a control logic figure 8.1 block diagram of 8-bit timer rev. 3.0, 09/98, page 161 of 361 8.1.3 input and output pins table 8.1 lists the input and output pins of the 8-bit timer. table 8.1 input and output pins of 8-bit timer abbreviation name tmr0 tmr1 i/o function timer output tmo 0 tmo 1 output output controlled by compare-match timer clock input tmci 0 tmci 1 input external clock source for the counter timer reset input tmri 0 tmri 1 input external reset signal for the counter 8.1.4 register configuration table 8.2 lists the registers of the 8-bit timer module. each channel has an independent set of registers. table 8.2 8-bit timer registers address name abbreviation r/w initial value tmr0 tmr1 timer control register tcr r/w h'00 h'ffc8 h'ffd0 timer control/status register tcsr r/(w) * h'10 h'ffc9 h'ffd1 timer constant register a tcora r/w h'ff h'ffca h'ffd2 timer constant register b tcorb r/w h'ff h'ffcb h'ffd3 timer counter tcnt r/w h'00 h'ffcc h'ffd4 serial/timer control register stcr r/w h'f8 h'ffd0 h'ffc3 note: softwar e can write a 0 to clear bits 7 to 5, but cannot write a 1 in these bits. rev. 3.0, 09/98, page 162 of 361 8.2 register descriptions 8.2.1 timer counter (tcnt) ? h'ffcc (tmr0), h'ffd4 (tmr1) bit:76543210 initial value: 0 0 0 0 0 0 0 0 read/write: r/w r/w r/w r/w r/w r/w r/w r/w each timer counter (tcnt) is an 8-bit up-counter that increments on a pulse generated from an internal or external clock source selected by clock select bits 2 to 0 (cks2 to cks0) of the timer control register (tcr). the cpu can always read or write the timer counter. the timer counter can be cleared by an external reset input or by an internal compare-match signal generated at a compare-match event. clock clear bits 1 and 0 (cclr1 and cclr0) of the timer control register select the method of clearing. when a timer counter overflows from h'ff to h'00, the overflow flag (ovf) in the timer control/status register (tcsr) is set to 1. the timer counters are initialized to h'00 at a reset and in the standby modes. 8.2.2 time constant registers a and b (tcora and tcorb) ? h'ffca and h'ffcb (tmr0), h'ffd2 and h'ffd3 (tmr1) bit:76543210 initial value: 1 1 1 1 1 1 1 1 read/write: r/w r/w r/w r/w r/w r/w r/w r/w tcora and tcorb are 8-bit readable/writable registers. the timer count is continually compared with the constants written in these registers. when a match is detected, the corresponding compare-match flag (cmfa or cmfb) is set in the timer control/status register (tcsr). the timer output signal (tmo0 or tmo1) is controlled by these compare-match signals as specified by output select bits 3 to 0 (os3 to os0) in the timer control/status register (tcsr). tcora and tcorb are initialized to h'ff at a reset and in the standby modes. rev. 3.0, 09/98, page 163 of 361 compare-match is not detected during the t 3 state of a write cycle to tcora or tcorb. see item (3) in section 8.6, application notes. 8.2.3 timer control register (tcr) ? h'ffc8 (tmr0), h'ffd0 (tmr1) bit:76543210 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 initial value: 0 0 0 0 0 0 0 0 read/write: r/w r/w r/w r/w r/w r/w r/w r/w each tcr is an 8-bit readable/writable register that selects the clock source and the time at which the timer counter is cleared, and enables interrupts. the tcrs are initialized to h'00 at a reset and in the standby modes. for timing diagrams, see section 8.3, operation. bit 7 ? compare-match interrupt enable b (cmieb): this bit selects whether to request compare-match interrupt b (cmib) when compare-match flag b (cmfb) in the timer control/status register (tcsr) is set to 1. bit 7 cmieb description 0 compare-match interrupt request b (cmib) is disabled. (initial value) 1 compare-match interrupt request b (cmib) is enabled. bit 6 ? compare-match interrupt enable a (cmiea): this bit selects whether to request compare-match interrupt a (cmia) when compare-match flag a (cmfa) in the timer control/status register (tcsr) is set to 1. bit 6 cmiea description 0 compare-match interrupt request a (cmia) is disabled. (initial value) 1 compare-match interrupt request a (cmia) is enabled. rev. 3.0, 09/98, page 164 of 361 bit 5 ? timer overflow interrupt enable (ovie): this bit selects whether to request a timer overflow interrupt (ovi) when the overflow flag (ovf) in the timer control/status register (tcsr) is set to 1. bit 5 ovie description 0 the timer overflow interrupt request (ovi) is disabled. (initial value) 1 the timer overflow interrupt request (ovi) is enabled. bits 4 and 3 ? counter clear 1 and 0 (cclr1 and cclr0): these bits select how the timer counter is cleared: by compare-match a or b or by an external reset input. bit 4 cclr1 bit 3 cclr0 description 0 0 not cleared. (initial value) 0 1 cleared on compare-match a. 1 0 cleared on compare-match b. 1 1 cleared on rising edge of external reset input signal. rev. 3.0, 09/98, page 165 of 361 bits 2, 1, and 0 ? clock select (cks2, cks1, and cks0): these bits and bits icks1 and icks0 in the serial/timer control register (stcr) select the internal or external clock source for the timer counter. six internal clock sources, derived by prescaling the system clock, are available for each timer channel. for internal clock sources the counter is incremented on the falling edge of the internal clock. for an external clock source, these bits can select whether to increment the counter on the rising or falling edge of the clock input, or on both edges. tcr stcr channel bit 2 cks2 bit 1 cks1 bit 0 cks0 bit 1 icks1 bit 0 icks0 description 0 000 ?? no clock source (timer stopped) (initial value) 001 ? 0 f /8 internal clock, counted on falling edge 001 ? 1 f /2 internal clock, counted on falling edge 010 ? 0 f /64 internal clock, counted on falling edge 010 ? 1 f /32 internal clock, counted on falling edge 011 ? 0 f /1024 internal clock, counted on falling edge 011 ? 1 f /256 internal clock, counted on falling edge 100 ?? no clock source (timer stopped) 101 ?? external clock source, counted on rising edge 110 ?? external clock source, counted on falling edge 111 ?? external clock source, counted on both rising and falling edges 1 000 ?? no clock source (timer stopped) (initial value) 0010 ?f /8 internal clock, counted on falling edge 0011 ?f /2 internal clock, counted on falling edge 0100 ?f /64 internal clock, counted on falling edge 0101 ?f /128 internal clock, counted on falling edge 0110 ?f /1024 internal clock, counted on falling edge 0111 ?f /2048 internal clock, counted on falling edge 100 ?? no clock source (timer stopped) 101 ?? external clock source, counted on rising edge 110 ?? external clock source, counted on falling edge 111 ?? external clock source, counted on both rising and falling edges rev. 3.0, 09/98, page 166 of 361 8.2.4 timer control/status register (tcsr) ? h'ffc9 (tmr0), h'ffd1 (tmr1) bit:76543210 cmfb cmfa ovf ? os3 os2 os1 os0 initial value: 0 0 0 1 0 0 0 0 read/write: r/(w) * r/(w) * r/(w) * ? r/w r/w r/w r/w note: software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits. the tcsr is an 8-bit readable and partially writable register that indicates compare-match and overflow status and selects the effect of compare-match events on the timer output signal. the tcsr is initialized to h'10 at a reset and in the standby modes. bit 7 ? compare-match flag b (cmfb): this status flag is set to 1 when the timer count matches the time constant set in tcorb. cmfb must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 7 cmfb description 0 to clear cmfb, the cpu must read cmfb after it has been set to 1, (initial value) then write a 0 in this bit. 1 this bit is set to 1 when tcnt = tcorb. bit 6 ? compare-match flag a (cmfa): this status flag is set to 1 when the timer count matches the time constant set in tcora. cmfa must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 6 cmfa description 0 to clear cmfa, the cpu must read cmfa after it has been set to 1, (initial value) then write a 0 in this bit. 1 this bit is set to 1 when tcnt = tcora. rev. 3.0, 09/98, page 167 of 361 bit 5 ? timer overflow flag (ovf): this status flag is set to 1 when the timer count overflows (changes from h'ff to h'00). ovf must be cleared by software. it is set by hardware, however, and cannot be set by software. bit 5 ovf description 0 to clear ovf, the cpu must read ovf after it has been set to 1, (initial value) then write a 0 in this bit. 1 this bit is set to 1 when tcnt changes from h'ff to h'00. bit 4 ? reserved: this bit is always read as 1. it cannot be written. bits 3 to 0 ? output select 3 to 0 (os3 to os0): these bits specify the effect of compare-match events on the timer output signal (tcor or tcnt). bits os3 and os2 control the effect of compare-match b on the output level. bits os1 and os0 control the effect of compare-match a on the output level. if compare-match a and b occur simultaneously, any conflict is resolved as explained in item (4) in section 8.6, application notes. after a reset, the timer output is 0 until the first compare-match event. when all four output select bits are cleared to 0 the timer output signal is disabled. bit 3 os3 bit 2 os2 description 0 0 no change when compare-match b occurs. (initial value) 01 output changes to 0 when compare-match b occurs. 1 0 output changes to 1 when compare-match b occurs. 1 1 output inverts (toggles) when compare-match b occurs. bit 1 os1 bit 0 os0 description 0 0 no change when compare-match a occurs. (initial value) 0 1 output changes to 0 when compare-match a occurs. 1 0 output changes to 1 when compare-match a occurs. 1 1 output inverts (toggles) when compare-match a occurs. rev. 3.0, 09/98, page 168 of 361 8.2.5 serial/timer control register (stcr) ? h'ffc3 bit:76543210 ????? mpe icks1 icks0 initial value: 1 1 1 1 1 0 0 0 read/write: ????? r/w r/w r/w the stcr is an 8-bit readable/writable register that controls the serial communication interface and selects internal clock sources for the timer counters. the stcr is initialized to h'f8 at a reset. bits 7 to 3 ? reserved: these bits cannot be modified and are always read as 1. bit 2 ? multiprocessor enable (mpe): controls the operating mode of serial communication interfaces 0 and 1. for details, see section 9, serial communication interface. bits 1 and 0 ? internal clock source select 1 and 0 (icks1 and icks0): these bits and bits cks2 to cks0 in the tcr select clock sources for the timer counters. for details, see section 8.2.3, timer control register. rev. 3.0, 09/98, page 169 of 361 8.3 operation 8.3.1 tcnt incrementation timing the timer counter increments on a pulse generated once for each period of the selected (internal or external) clock source. internal clock: internal clock sources are created from the system clock by a prescaler. the counter increments on an internal tcnt clock pulse generated from the falling edge of the prescaler output, as shown in figure 8.2. bits cks2 to cks0 of the tcr and bits icks1 and icks0 of the stcr can select one of the six internal clocks. n n - 1 n + 1 internal clock tcnt clock pulse ? tcnt figure 8.2 count timing for internal clock input external clock: if external clock input (tmci) is selected, the timer counter can increment on the rising edge, the falling edge, or both edges of the external clock signal. figure 8.3 shows incrementation on both edges of the external clock signal. the external clock pulse width must be at least 1.5 system clock periods for incrementation on a single edge, and at least 2.5 system clock periods for incrementation on both edges. see figure 8.4. the counter will not increment correctly if the pulse width is shorter than these values. rev. 3.0, 09/98, page 170 of 361 n n - 1 n + 1 external clock source tcnt clock pulse ? tcnt figure 8.3 count timing for external clock input 8.3.2 compare match timing (1) setting of compare-match flags a and b (cmfa and cmfb): the compare-match flags are set to 1 by an internal compare-match signal generated when the timer count matches the time constant in tcnt or tcor. the compare-match signal is generated at the last state in which the match is true, just before the timer counter increments to a new value. accordingly, when the timer count matches one of the time constants, the compare-match signal is not generated until the next period of the clock source. figure 8.4 shows the timing of the setting of the compare-match flags. n n n + 1 tcnt ? tcor internal compare-match signal cmf figure 8.4 setting of compare-match flags rev. 3.0, 09/98, page 171 of 361 (2) output timing: when a compare-match event occurs, the timer output (tmo0 or tmo1) changes as specified by the output select bits (os3 to os0) in the tcsr. depending on these bits, the output can remain the same, change to 0, change to 1, or toggle. figure 8.5 shows the timing when the output is set to toggle on compare-match a. internal compare-match a signal timer output (tmo) ? figure 8.5 timing of timer output (3) timing of compare-match clear: depending on the cclr1 and cclr0 bits in the tcr, the timer counter can be cleared when compare-match a or b occurs. figure 8.6 shows the timing of this operation. n n' 00 internal compare-match signal tcnt ? figure 8.6 timing of compare-match clear rev. 3.0, 09/98, page 172 of 361 8.3.3 external reset of tcnt when the cclr1 and cclr0 bits in the tcr are both set to 1, the timer counter is cleared on the rising edge of an external reset input. figure 8.7 shows the timing of this operation. the timer reset pulse width must be at least 1.5 system clock periods. n n - 1 n' 00 external reset input (tmri) internal clear pulse ? tcnt figure 8.7 timing of external reset 8.3.4 setting of tcsr overflow flag (ovf) the overflow flag (ovf) is set to 1 when the timer count overflows (changes from h'ff to h'00). figure 8.8 shows the timing of this operation. h' ff h' 00 tcnt ? internal overflow signal ovf figure 8.8 setting of overflow flag (ovf) rev. 3.0, 09/98, page 173 of 361 8.4 interrupts each channel in the 8-bit timer can generate three types of interrupts: compare-match a and b (cmia and cmib), and overflow (ovi). each interrupt is requested when the corresponding enable bits are set in the tcr and tcsr. independent signals are sent to the interrupt controller for each interrupt. table 8.3 lists information about these interrupts. table 8.3 8-bit timer interrupts interrupt description priority cmia requested when cmfa and cmiea are set high cmib requested when cmfb and cmieb are set ovi requested when ovf and ovie are set low 8.5 sample application in the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle. the control bits are set as follows: (1) in the tcr, cclr1 is cleared to 0 and cclr0 is set to 1 so that the timer counter is cleared when its value matches the constant in tcora. (2) in the tcsr, bits os3 to os0 are set to 0110, causing the output to change to 1 on compare-match a and to 0 on compare-match b. with these settings, the 8-bit timer provides output of pulses at a rate determined by tcora with a pulse width determined by tcorb. no software intervention is required. tcnt h'ff tcora tcotb h'00 tmo pin clear counter figure 8.9 example of pulse output rev. 3.0, 09/98, page 174 of 361 8.6 application notes application programmers should note that the following types of contention can occur in the 8-bit timer. (1) contention between tcnt write and clear: if an internal counter clear signal is generated during the t 3 state of a write cycle to the timer counter, the clear signal takes priority and the write is not performed. figure 8.10 shows this type of contention. ? internal address bus internal write signal counter clear signal tcnt write cycle: cpu writes to tcnt t 1 t 2 t 3 h' 00 n tcnt address figure 8.10 tcnt write-clear contention rev. 3.0, 09/98, page 175 of 361 (2) contention between tcnt write and increment: if a timer counter increment pulse is generated during the t 3 state of a write cycle to the timer counter, the write takes priority and the timer counter is not incremented. figure 8.11 shows this type of contention. ? internal address bus internal write signal tcnt clock pulse tcnt write cycle: cpu writes to tcnt t 1 t 2 t 3 write data nm tcnt address figure 8.11 tcnt write-increment contention rev. 3.0, 09/98, page 176 of 361 (3) contention between tcor write and compare-match: if a compare-match occurs during the t 3 state of a write cycle to tcora or tcorb, the write takes precedence and the compare-match signal is inhibited. figure 8.12 shows this type of contention. ? internal address bus internal write signal tcnt tcora or tcorb compare-match a or b signal write cycle: cpu writes to tcora or tcorb t 1 t 2 t 3 n + 1 n tcor write data inhibited nm tcor address figure 8.12 contention between tcor write and compare-match (4) contention between compare-match a and compare-match b: if identical time constants are written in tcora and tcorb, causing compare-match a and b to occur simultaneously, any conflict between the output selections for compare-match a and b is resolved by following the priority order in table 8.4. table 8.4 priority of timer output output selection priority toggle high 1 output 0 output no change low rev. 3.0, 09/98, page 177 of 361 (5) incrementation caused by changing of internal clock source: when an internal clock source is changed, the changeover may cause the timer counter to increment. this depends on the time at which the clock select bits (cks1, cks0) are rewritten, as shown in table 8.5. the pulse that increments the timer counter is generated at the falling edge of the internal clock source signal. if clock sources are changed when the old source is high and the new source is low, as in case no. 3 in table 8.5, the changeover generates a falling edge that triggers the tcnt clock pulse and increments the timer counter. switching between an internal and external clock source can also cause the timer counter to increment. table 8.5 effect of changing internal clock sources no. description timing chart 1 low ? low * 1 : clock select bits are rewritten while both clock sources are low. old clock source new clock source tcnt clock pulse tcnt cks rewrite n n + 1 2 low ? high * 2 : clock select bits are rewritten while old clock source is low and new clock source is high. old clock source new clock source tcnt clock pulse tcnt cks rewrite n n + 1 n + 2 notes: 1. including a transition from low to the stopped state (cks1 = 0, cks0 = 0), or a transition from the stopped state to low. 2. including a transition from the stopped state to high. rev. 3.0, 09/98, page 178 of 361 table 8.5 effect of changing internal clock sources (cont) no. description timing chart 3 high ? low * 1 : clock select bits are rewritten while old clock source is high and new clock source is low. old clock source new clock source tcnt clock pulse tcnt n n + 1 n + 2 cks rewrite * 2 4 high ? high: clock select bits are rewritten while both clock sources are high. old clock source new clock source tcnt clock pulse tcnt n n + 1 cks rewrite n + 2 notes: 1. including a transition from high to the stopped state. 2. the switching of clock sources is regarded as a falling edge that increments the tcnt. rev. 3.0, 09/98, page 179 of 361 section 9 pwm timers 9.1 overview the h8/338 series has an on-chip pulse-width modulation (pwm) timer module with two independent channels (pwm0 and pwm1). both channels are functionally identical. each pwm channel generates a rectangular output pulse with a duty cycle of 0 to 100%. the duty cycle is specified in an 8-bit duty register (dtr). 9.1.1 features the pwm timer module has the following features: selection of eight clock sources duty cycles from 0 to 100% with 1/250 resolution output with positive or negative logic and software enable/disable control rev. 3.0, 09/98, page 180 of 361 9.1.2 block diagram figure 9.1 shows a block diagram of one pwm timer channel. pulse dtr output control comparator tcnt tcr internal data bus internal clock sources clock clock select compare-match dtr tcnt tcr legend: : timer control register (8 bits) : duty register (8 bits) : times counter (8 bits) ?/2 ?/8 ?/32 ?/128 ?/256 ?/1024 ?/2048 ?/4096 module data bus bus interface figure 9.1 block diagram of pwm timer rev. 3.0, 09/98, page 181 of 361 9.1.3 input and output pins table 9.1 lists the output pins of the pwm timer module. there are no input pins. table 9.1 output pins of pwm timer module name abbreviation i/o function pwm0 output pw0 output pulse output from pwm timer channel 0. pwm1 output pw1 output pulse output from pwm timer channel 1. 9.1.4 register configuration the pwm timer module has three registers for each channel as listed in table 9.2. table 9.2 pwm timer registers address name abbreviation r/w initial value pwm0 pwm1 timer control register tcr r/w h'38 h'ffa0 h'ffa4 duty register dtr r/w h'ff h'ffa1 h'ffa5 timer counter tcnt r/w h'00 h'ffa2 h'ffa6 9.2 register descriptions 9.2.1 timer counter (tcnt) ? h'ffa2 (pwm0), h'ffa6 (pwm1) bit:76543210 initial value: 0 0 0 0 0 0 0 0 read/write: r/w r/w r/w r/w r/w r/w r/w r/w the pwm timer counters (tcnt) are 8-bit up-counters. when the output enable bit (oe) in the timer control register (tcr) is set to 1, the timer counter starts counting pulses of an internal clock source selected by clock select bits 2 to 0 (cks2 to cks0). after counting from h'00 to h'f9, the timer counter repeats from h'00. the pwm timer counters are initialized to h'00 at a reset and in the standby modes, and when the oe bit is cleared to 0. rev. 3.0, 09/98, page 182 of 361 9.2.2 duty register (dtr) ? h'ffa1 (pwm0), h'ffa5 (pwm1) bit:76543210 initial value: 1 1 1 1 1 1 1 1 read/write: r/w r/w r/w r/w r/w r/w r/w r/w the duty registers (dtr) are 8-bit readable/writable registers that specify the duty cycle of the output pulse. any duty cycle from 0 to 100% can be selected, with a resolution of 1/250. writing 0 (h'00) in a dtr gives a 0% duty cycle; writing 125 (h'7d) gives a 50% duty cycle; writing 250 (h'fa) gives a 100% duty cycle. the timer count is continually compared with the dtr contents. if the dtr value is not 0, when the count increments from h'00 to h'01 the pwm output signal is set to 1. when the count increments past the dtr value, the pwm output returns to 0. if the dtr value is 0 (0% duty), the pwm output remains constant at 0. the dtrs are double-buffered. a new value written in a dtr while the timer counter is running does not become valid until after the count changes from h'f9 to h'00. when the timer counter is stopped (while the oe bit is 0), new values become valid as soon as written. when a dtr is read, the value read is the currently valid value. the dtrs are initialized to h'ff at a reset and in the standby modes. 9.2.3 timer control register (tcr) ? h'ffa0 (pwm0), h'ffa4 (pwm1) bit:76543210 oe os ??? cks2 cks1 cks0 initial value: 0 0 1 1 1 0 0 0 read/write: r/w r/w ??? r/w r/w r/w the tcrs are 8-bit readable/writable registers that select the clock source and control the pwm outputs. the tcrs are initialized to h'38 at a reset and in the standby modes. rev. 3.0, 09/98, page 183 of 361 bit 7 ? output enable (oe): this bit enables the timer counter and the pwm output. bit 7 oe description 0 pwm output is disabled. tcnt is cleared to h'00 and stopped. (initial value) 1 pwm output is enabled. tcnt runs. bit 6 ? output select (os): this bit selects positive or negative logic for the pwm output. bit 6 os description 0 positive logic; positive-going pwm pulse, 1 = high (initial value) 1 negative logic; negative-going pwm pulse, 1 = low bits 5 to 3 ? reserved: these bits cannot be modified and are always read as 1. bits 2, 1, and 0 ? clock select (cks2, cks1, and cks0): these bits select one of eight internal clock sources obtained by dividing the system clock ( f ). bit 2 cks2 bit 1 cks1 bit 0 cks0 description 000 f /2 (initial value) 001 f /8 010 f /32 011 f /128 100 f /256 101 f /1024 110 f /2048 111 f /4096 from the clock source frequency, the resolution, period, and frequency of the pwm output can be calculated as follows. resolution = 1/clock source frequency pwm period = resolution 250 pwm frequency = 1/pwm period if the system clock frequency is 10mhz, then the resolution, period, and frequency of the pwm output for each clock source are given in table 9.3. rev. 3.0, 09/98, page 184 of 361 table 9.3 pwm timer parameters for 10mhz system clock internal clock frequency resolution pwm period pwm frequency f /2 200ns 50s 20khz f /8 800ns 200s 5khz f /32 3.2s 800s 1.25khz f /128 12.8s 3.2ms 312.5hz f /256 25.6s 6.4ms 156.3hz f /1024 102.4s 25.6ms 39.1hz f /2048 204.8s 51.2ms 19.5hz f /4096 409.6s 102.4ms 9.8hz 9.3 operation 9.3.1 timer incrementation the pwm clock source is created from the system clock ( f ) by a prescaler. the timer counter increments on a tcnt clock pulse generated from the falling edge of the prescaler output as shown in figure 9.2. n n - 1 n + 1 prescaler output tcnt clock pulse ? tcnt figure 9.2 tcnt increment timing rev. 3.0, 09/98, page 185 of 361 9.3.2 pwm operation figure 9.3 is a timing chart of the pwm operation. n (a) h' 00 (b) h' 01 h' 02 h' f9 (d) h' 00 h' 01 n h' ff (d) m n C 1 n + 1 (c) (c) (b) (a) (e) tcnt clock pulses oe ? tcnt dtr ( os = 0 ) pwm output n written in dtr pwm 1 cycle ( os = 1 ) m written in dtr note: * used for port 4 input/output: state depends on values in data register and data direction register. figure 9.3 pwm timing (1) positive logic (os = 0) ? when (oe = 0) - (a) in figure 9.3: the timer count is held at h'00 and pwm output is inhibited. [pin 4 6 (for pw0) or pin 4 7 (for pw1) is used for port 4 input/output, and its state depends on the corresponding port 4 data register and data direction register.] any value (such as n in figure 9.3) written in the dtr becomes valid immediately. - when (oe = 1) i) the timer counter begins incrementing. the pwm output goes high when tcnt changes from h'00 to h'01, unless dtr = h'00. [(b) in figure 9.3] ii) when the count passes the dtr value, the pwm output goes low. [(c) in figure 9.3] rev. 3.0, 09/98, page 186 of 361 iii) if the dtr value is changed (by writing the data m in figure 9.3), the new value becomes valid after the timer count changes from h'f9 to h'00. [(d) in figure 9.3] (2) negative logic (os = 1) - (e) in figure 9.3: the operation is the same except that high and low are reversed in the pwm output. [(e) in figure 9.3] 9.4 application notes some notes on the use of the pwm timer module are given below. (1) any necessary changes to the clock select bits (cks2 to cks0) and output select bit (os) should be made before the output enable bit (oe) is set to 1. (2) if the dtr value is h'00, the duty cycle is 0% and pwm output remains constant at 0. if the dtr value is h'fa to h'ff, the duty cycle is 100% and pwm output remains constant at 1. (for positive logic, 0 is low and 1 is high. for negative logic, 0 is high and 1 is low.) rev. 3.0, 09/98, page 187 of 361 section 10 serial communication interface 10.1 overview the h8/338 series includes two serial communication interface channels (sci0 and sci1) for transferring serial data to and from other chips. either synchronous or asynchronous communication can be selected. 10.1.1 features the features of the on-chip serial communication interface are: asynchronous mode the h8/338 series can communicate with a uart (universal asynchronous receiver/transmitter), acia (asynchronous communication interface adapter), or other chip that employs standard asynchronous serial communication. it also has a multiprocessor communication function for communication with other processors. twelve data formats are available. ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even, odd, or none ? multiprocessor bit: 1 or 0 ? error detection: parity, overrun, and framing errors ? break detection: when a framing error occurs, the break condition can be detected by reading the level of the rxd line directly. synchronous mode the sci can communicate with chips able to perform clocked synchronous data transfer. ? data length: 8 bits ? error detection: overrun errors full duplex communication the transmitting and receiving sections are independent, so each channel can transmit and receive simultaneously. both the transmit and receive sections use double buffering, so continuous data transfer is possible in either direction. built-in baud rate generator any specified baud rate can be generated. internal or external clock source the sci can operate on an internal clock signal from the baud rate generator, or an external clock signal input at the sck0 or sck1 pin. four interrupts rev. 3.0, 09/98, page 188 of 361 tdr-empty, tsr-empty, receive-end, and receive-error interrupts are requested independently. 10.1.2 block diagram figure 10.1 shows a block diagram of one serial communication interface channel. rdr r x d t x d sck tdr rsr tsr ssr scr smr communication control baud rate generator internal data bus internal clock rdr rsr tdr tsr ssr scr smr brr legend: : receive shift register (8 bits) : receive data register (8 bits) : transmit shift register (8 bits) : transmit data register (8 bits) : serial mode register (8 bits) : serial control register (8 bits) : serial status register (8 bits) : bit rate register (8 bits) module data bus ? ?/4 ?/16 ?/64 external clock source clock parity generate parity check interrupt signals tei txi rxi eri brr bus interface figure 10.1 block diagram of serial communication interface 10.1.3 input and output pins table 10.1 lists the input and output pins used by the sci module. rev. 3.0, 09/98, page 189 of 361 table 10.1 sci input/output pins channel name abbr. i/o function 0 serial clock sck 0 input/output serial clock input and output. receive data rxd 0 input receive data input. transmit data txd 0 output transmit data output. 1 serial clock sck 1 input/output serial clock input and output. receive data rxd 1 input receive data input. transmit data txd 1 output transmit data output. 10.1.4 register configuration table 10.2 lists the sci registers. these registers specify the operating mode (synchronous or asynchronous), data format and bit rate, and control the transmit and receive sections. table 10.2 sci registers channel name abbr. r/w value address 0 receive shift register rsr ??? receive data register rdr r h'00 h'ffdd transmit shift register tsr ??? transmit data register tdr r/w h'ff h'ffdb serial mode register smr r/w h'00 h'ffd8 serial control register scr r/w h'00 h'ffda serial status register ssr r/(w) * h'84 h'ffdc bit rate register brr r/w h'ff h'ffd9 1 receive shift register rsr ??? receive data register rdr r h'00 h'ff8d transmit shift register tsr ??? transmit data register tdr r/w h'ff h'ff8b serial mode register smr r/w h'00 h'ff88 serial control register scr r/w h'00 h'ff8a serial status register ssr r/(w) * h'84 h'ff8c bit rate register brr r/w h'ff h'ff89 0 and 1 serial/timer control register stcr r/w h'f8 h'ffc3 note: software can write a 0 to clear the flags in bits 7 to 3, but cannot write 1 in these bits. rev. 3.0, 09/98, page 190 of 361 10.2 register descriptions 10.2.1 receive shift register (rsr) bit:76543210 read/write: ???????? the rsr is a shift register that converts incoming serial data to parallel data. when one data character has been received, it is transferred to the receive data register (rdr). the cpu cannot read or write the rsr directly. 10.2.2 receive data register (rdr) ? h'ffdd, h'ff8d bit:76543210 initial value: 0 0 0 0 0 0 0 0 read/write: r r r r r r r r the rdr stores received data. as each character is received, it is transferred from the rsr to the rdr, enabling the rsr to receive the next character. this double-buffering allows the sci to receive data continuously. the cpu can read but not write the rdr. the rdr is initialized to h'00 at a reset and in the standby modes. 10.2.3 transmit shift register (tsr) bit:76543210 read/write: ???????? the tsr is a shift register that converts parallel data to serial transmit data. when transmission of this character is completed, the next character is moved from the transmit data register (tdr) to the tsr and transmission of that character begins. if the tdre bit is still set to 1, however, nothing is transferred to the tsr. the cpu cannot read or write the tsr directly. rev. 3.0, 09/98, page 191 of 361 10.2.4 transmit data register (tdr) ? h'ffdb, h'ff8b bit:76543210 initial value: 1 1 1 1 1 1 1 1 read/write: r/w r/w r/w r/w r/w r/w r/w r/w the tdr is an 8-bit readable/writable register that holds the next character to be transmitted. when the tsr becomes empty, the character written in the tdr is transferred to the tsr. continuous data transmission is possible by writing the next byte in the tdr while the current byte is being transmitted from the tsr. the tdr is initialized to h'ff at a reset and in the standby modes. 10.2.5 serial mode register (smr) ? h'ffd8, h'ff88 bit:76543210 c/ a chr pe o/ e stop mp cks1 cks0 initial value: 1 0 0 0 0 0 0 0 read/write: r/w r/w r/w r/w r/w r/w r/w r/w the smr is an 8-bit readable/writable register that controls the communication format and selects the clock rate for the internal clock source. it is initialized to h'00 at a reset and in the standby modes. for further information on the smr settings and communication formats, see tables 10.5 and 10.7 in section 10.3, operation. bit 7 ? communication mode (c/a): this bit selects the asynchronous or clocked synchronous communication mode. bit 7 c/a description 0 asynchronous communication. (initial value) 1 clocked synchronous communication. rev. 3.0, 09/98, page 192 of 361 bit 6 ? character length (chr): this bit selects the character length in asynchronous mode. it is ignored in synchronous mode. bit 6 chr description 0 8 bits per character. (initial value) 1 7 bits per character. (bits 0 to 6 of tdr and rdr are used for transmitting and receiving, respectively.) bit 5 ? parity enable (pe): this bit selects whether to add a parity bit in asynchronous mode. it is ignored in synchronous mode, and when a multiprocessor format is used. bit 5 pe description 0 transmit: no parity bit is added. (initial value) receive: parity is not checked. 1 transmit: a parity bit is added. receive: parity is checked. bit 4 ? parity mode (o/e ): in asynchronous mode, when parity is enabled (pe = 1), this bit selects even or odd parity. even parity means that a parity bit is added to the data bits for each character to make the total number of 1s even. odd parity means that the total number of 1s is made odd. this bit is ignored when pe = 0, or when a multiprocessor format is used. it is also ignored in the synchronous mode. bit 4 o/e description 0 even parity. (initial value) 1 odd parity. rev. 3.0, 09/98, page 193 of 361 bit 3 ? stop bit length (stop): this bit selects the number of stop bits. it is ignored in the synchronous mode. bit 3 stop description 0 one stop bit. (initial value) transmit: one stop bit is added. receive: one stop bit is checked to detect framing errors. 1 two stop bits. transmit: two stop bits are added. receive: the first stop bit is checked to detect framing errors. if the second stop bit is a space (0), it is regarded as the next start bit. bit 2 ? multiprocessor mode (mp): this bit selects the multiprocessor format in asynchronous communication. when multiprocessor format is selected, the parity settings of the parity enable bit (pe) and parity mode bit (o/ e ) are ignored. the mp bit is ignored in synchronous communication. the mp bit is valid only when the mpe bit in the serial/timer control register (stcr) is set to 1. when the mpe bit is cleared to 0, the multiprocessor communication function is disabled regardless of the setting of the mp bit. bit 2 mp description 0 multiprocessor communication function is disabled. (initial value) 1 multiprocessor communication function is enabled. bits 1 and 0 ? clock select 1 and 0 (cks1 and cks0): these bits select the internal clock source when the baud rate generator is clocked from within the chip. bit 1 cks1 bit 0 cks0 description 00 f clock (initial value) 01 f /4 clock 10 f /16 clock 11 f /64 clock rev. 3.0, 09/98, page 194 of 361 10.2.6 serial control register (scr) ? h'ffda, h'ff8a bit:76543210 tie rie te re mpie teie cke1 cke0 initial value: 0 0 0 0 0 0 0 0 read/write: r/w r/w r/w r/w r/w r/w r/w r/w the scr is an 8-bit readable/writable register that enables or disables various sci functions. it is initialized to h'00 at a reset and in the standby modes. bit 7 ? transmit interrupt enable (tie): this bit enables or disables the tdr-empty interrupt (txi) requested when the transmit data register empty (tdre) bit in the serial status register (ssr) is set to 1. bit 7 tie description 0 the tdr-empty interrupt request (txi) is disabled. (initial value) 1 the tdr-empty interrupt request (txi) is enabled. bit 6 ? receive interrupt enable (rie): this bit enables or disables the receive-end interrupt (rxi) requested when the receive data register full (rdrf) bit in the serial status register (ssr) is set to 1, and the receive error interrupt (eri) requested when the overrun error (orer), framing error (fer), or parity error (per) bit in the serial status register (ssr) is set to 1. bit 6 rie description 0 the receive-end interrupt (rxi) and receive-error (eri) requests are (initial value) disabled. 1 the receive-end interrupt (rxi) and receive-error (eri) requests are enabled. bit 5 ? transmit enable (te): this bit enables or disables the transmit function. when the transmit function is enabled, the txd pin is automatically used for output. when the transmit function is disabled, the txd pin can be used as a general-purpose i/o port. bit 5 te description 0 the transmit function is disabled. (initial value) the txd pin can be used for general-purpose i/o. 1 the transmit function is enabled. the txd pin is used for output. rev. 3.0, 09/98, page 195 of 361 bit 4 ? receive enable (re): this bit enables or disables the receive function. when the receive function is enabled, the rxd pin is automatically used for input. when the receive function is disabled, the rxd pin is available as a general-purpose i/o port. bit 4 re description 0 the receive function is disabled. the rxd pin can be (initial value) used for general-purpose i/o. 1 the receive function is enabled. the rxd pin is used for input. bit 3 ? multiprocessor interrupt enable (mpie): when serial data are received in a multiprocessor format, this bit enables or disables the receive-end interrupt (rxi) and receive-error interrupt (eri) until data with the multiprocessor bit set to 1 are received. it also enables or disables the transfer of received data from the rsr to the rdr, and enables or disables setting of the rdrf, fer, per, and orer bits in the serial status register (ssr). the mpie bit is ignored when the mp bit is cleared to 0, and in synchronous mode. clearing the mpie bit to 0 disables the multiprocessor receive interrupt function. in this condition data are received regardless of the value of the multiprocessor bit in the receive data. setting the mpie bit to 1 enables the multiprocessor receive interrupt function. in this condition, if the multiprocessor bit in the receive data is 0, the receive-end interrupt (rxi) and receive-error interrupt (eri) are disabled, the receive data are not transferred from the rsr to the rdr, and the rdrf, fer, per, and orer bits in the serial status register (ssr) are not set. if the multiprocessor bit is 1, however, the mpb bit in the ssr is set to 1, the mpie bit is cleared to 0, the receive data are transferred from the rsr to the rdr, the fer, per, and orer bits can be set, and the receive-end and receive-error interrupts are enabled. bit 3 mpie description 0 the multiprocessor receive interrupt function is disabled. (initial value) (normal receive operation) 1 the multiprocessor receive interrupt function is enabled. during the interval before data with the multiprocessor bit set to 1 are received, the receive interrupt request (rxi) and receive-error interrupt request (eri) are disabled, the rdrf, fer, per, and orer bits are not set in the serial status register (ssr), and no data are transferred from the rsr to the rdr. the mpie bit is cleared at the following times: (1) when 0 is written in mpie. (2) when data with the multiprocessor bit set to 1 are received. rev. 3.0, 09/98, page 196 of 361 bit 2 ? transmit-end interrupt enable (teie): this bit enables or disables the tsr-empty interrupt (tei) requested when the transmit-end bit (tend) in the serial status register (ssr) is set to 1. bit 2 teie description 0 the tsr-empty interrupt request (tei) is disabled. (initial value) 1 the tsr-empty interrupt request (tei) is enabled. bit 1 ? clock enable 1 (cke1): this bit selects the internal or external clock source for the baud rate generator. when the external clock source is selected, the sck pin is automatically used for input of the external clock signal. bit 1 cke1 description 0 internal clock source. (initial value) when c/ a = 1, the serial clock signal is output at the sck pin. when c/ a = 0, output depends on the cke0 bit. 1 external clock source. the sck pin is used for input. bit 0 ? clock enable 0 (cke0): when an internal clock source is used in asynchronous mode, this bit enables or disables serial clock output at the sck pin. this bit is ignored when the external clock is selected, or when synchronous mode is selected. for further information on the communication format and clock source selection, see table 10.7 in section 10.3, operation. bit 0 cke0 description 0 the sck pin is not used by the sci (and is available as a (initial value) general-purpose i/o port). 1 the sck pin is used for serial clock output. rev. 3.0, 09/98, page 197 of 361 10.2.7 serial status register (ssr) ? h'ffdc, h'ff8c bit:76543210 tdre rdrf orer fer per tend mpb mpbt initial value: 1 0 0 0 0 1 0 0 read/write: r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * rrr/w note: soft ware can write a 0 to clear the flags, but cannot write a 1 in these bits. the ssr is an 8-bit register that indicates transmit and receive status. it is initialized to h'84 at a reset and in the standby modes. bit 7 ? transmit data register empty (tdre): this bit indicates when the tdr contents have been transferred to the tsr and the next character can safely be written in the tdr. bit 7 tdre description 0 to clear tdre, the cpu must read tdre after it has been set to 1, then write a 0 in this bit. 1 this bit is set to 1 at the following times: (initial value) (1) when tdr contents are transferred to the tsr. (2) when the te bit in the scr is cleared to 0. bit 6 ? receive data register full (rdrf): this bit indicates when one character has been received and transferred to the rdr. bit 6 rdrf description 0 to clear rdrf, the cpu must read rdrf after it has been set to 1, (initial value) then write a 0 in this bit. 1 this bit is set to 1 when one character is received without error and transferred from the rsr to the rdr. bit 5 ? overrun error (orer): this bit indicates an overrun error during reception. bit 5 orer description 0 to clear orer, the cpu must read orer after it has been set to 1, (initial value) then write a 0 in this bit. 1 this bit is set to 1 if reception of the next character ends while the receive data register is still full (rdrf = 1). rev. 3.0, 09/98, page 198 of 361 bit 4 ? framing error (fer): this bit indicates a framing error during data reception in asynchronous mode. it has no meaning in synchronous mode. bit 4 fer description 0 to clear fer, the cpu must read fer after it has been set to 1, (initial value) then write a 0 in this bit. 1 this bit is set to 1 if a framing error occurs (stop bit = 0). bit 3 ? parity error (per): this bit indicates a parity error during data reception in the asynchronous mode, when a communication format with parity bits is used. this bit has no meaning in the synchronous mode, or when a communication format without parity bits is used. bit 3 per description 0 to clear per, the cpu must read per after it has been set to 1, (initial value) then write a 0 in this bit. 1 this bit is set to 1 when a parity error occurs (the parity of the received data does not match the parity selected by the o/ e bit in smr). bit 2 ? transmit end (tend): this bit indicates that the serial communication interface has stopped transmitting because there was no valid data in the tdr when the last bit of the current character was transmitted. the tend bit is also set to 1 when the te bit in the serial control register (scr) is cleared to 0. the tend bit can be read but not written. to clear tend to 0, software must read the serial status register while tdre = 1, then write 0 in tdre. bit 2 tend description 0 to clear tend, the cpu must read tdre after it has been set to 1, (initial value) then write a 0 in tdre. 1 this bit is set to 1 when: (1) te = 0 (2) tdre = 1 at the end of transmission of a character rev. 3.0, 09/98, page 199 of 361 bit 1 ? multiprocessor bit (mpb): stores the value of the multiprocessor bit in data received in a multiprocessor format in asynchronous communication mode. this bit is cleared to 0 in synchronous mode, or when a multiprocessor format is not used. if the re bit is cleared to 0 when a multiprocessor format is used, the mpb bit retains its previous value. mpb can be read but not written. bit 1 mpb description 0 multiprocessor bit = 0 in receive data. (initial value) 1 multiprocessor bit = 1 in receive data. bit 0 ? multiprocessor bit transfer (mpbt): stores the value of the multiprocessor bit inserted in transmit data when a multiprocessor format is used in asynchronous communication mode. the mpbt bit has no effect in synchronous mode, or when a multiprocessor format is not used. it is not used in receiving data. bit 0 mpbt description 0 multiprocessor bit = 0 in transmit data. (initial value) 1 multiprocessor bit = 1 in transmit data. rev. 3.0, 09/98, page 200 of 361 10.2.8 bit rate register (brr) ? h'ffd9, h'ff89 bit:76543210 initial value: 1 1 1 1 1 1 1 1 read/write: r/w r/w r/w r/w r/w r/w r/w r/w the brr is an 8-bit register that, together with the cks1 and cks0 bits in the smr, determines the baud rate output by the baud rate generator. the brr is initialized to h'ff (the slowest rate) at a reset and in the standby modes. tables 10.3 and 10.4 show examples of brr (n) and cks (n) settings for commonly used bit rates. table 10.5 lists the maximum bit rates in asynchronous mode. table 10.3 examples of brr settings in asynchronous mode (1) xtal frequency (mhz) 2 2.4576 4 4.194304 bit rate n n error (%) n n error (%) n n error (%) n n error (%) 110 1 70 +0.03 1 86 +0.31 1 141 +0.03 1 148 - 0.04 150 0 207 +0.16 0 255 0 1 103 +0.16 1 108 +0.21 300 0 103 +0.16 0 127 0 0 207 +0.16 0 217 +0.21 600 0 51 +0.16 0 63 0 0 103 +0.16 0 108 +0.21 1200 0 25 +0.16 0 31 0 0 51 +0.16 0 54 - 0.70 2400 0 12 +0.16 0 15 0 0 25 +0.16 0 26 +1.14 4800 ??? 070012+0.16013 - 2.48 9600 ??? 030 ??? 06 - 2.48 19200 ??? 010 ?????? 31250 0 0 0 ??? 010 ??? 38400 ??? 000 ?????? rev. 3.0, 09/98, page 201 of 361 table 10.3 examples of brr settings in asynchronous mode (2) xtal frequency (mhz) 4.9152 6 7.3728 8 bit rate n n error (%) n n error (%) n n error (%) n n error (%) 110 1 174 - 0.26 2 52 +0.50 2 64 +0.70 2 70 +0.03 150 1 127 0 1 155 +0.16 1 191 0 1 207 +0.16 300 0 255 0 1 77 +0.16 1 95 0 1 103 +0.16 600 0 127 0 0 155 +0.16 0 191 0 0 207 +0.16 1200 0 63 0 0 77 +0.16 0 95 0 0 103 +0.16 2400 0 31 0 0 38 +0.16 0 47 0 0 51 +0.16 4800 0 15 0 0 19 - 2.34 0 23 0 0 25 +0.16 9600 07009 - 2.34 0 11 0 0 12 +0.16 19200 03004 - 2.34 0 5 0 ??? 31250 ??? 020 ??? 030 38400 0 1 0 ??? 020 ??? table 10.3 examples of brr settings in asynchronous mode (3) xtal frequency (mhz) 9.8304 10 12 12.288 bit rate n n error (%) n n error (%) n n error (%) n n error (%) 110 2 86 +0.31 2 88 - 0.25 2 106 - 0.44 2 108 +0.08 150 1 255 0 2 64 +0.16 2 77 +0.16 2 79 0 300 1 127 0 1 129 +0.16 1 155 +0.16 1 159 0 600 0 255 0 1 64 +0.16 1 77 +0.16 1 79 0 1200 0 127 0 0 129 +0.16 0 155 +0.16 0 159 0 2400 0 63 0 0 64 +0.16 0 77 +0.16 0 79 0 4800 0 31 0 0 32 - 1.36 0 38 +0.16 0 39 0 9600 0 15 0 0 15 +1.73 0 19 - 2.34 0 19 0 19200 07007+1.7309 - 2.34 0 9 0 31250 0 4 - 1.7004005005+2.40 38400 03003+1.7304 - 2.34 0 4 0 rev. 3.0, 09/98, page 202 of 361 table 10.3 examples of brr settings in asynchronous mode (4) xtal frequency (mhz) 14.7456 16 19.6608 20 bit rate n n error (%) n n error (%) n n error (%) n n error (%) 110 2 130 - 0.07 2 141 +0.03 2 174 - 0.26 2 177 - 0.25 150 2 95 0 2 103 +0.16 2 127 0 2 129 +0.16 300 1 191 0 1 207 +0.16 1 255 0 2 64 +0.16 600 1 95 0 1 103 +0.16 1 127 0 1 129 +0.16 1200 0 191 0 0 207 +0.16 0 255 0 1 64 +0.16 2400 0 95 0 0 103 +0.16 0 127 0 0 129 +0.16 4800 0 47 0 0 51 +0.16 0 63 0 0 64 +0.16 9600 0 23 0 0 25 +0.16 0 31 0 0 32 - 1.36 19200 0 11 0 0 12 +0.16 0 15 0 0 15 +1.73 31250 ??? 07009 - 1.70 0 9 0 38400 0 5 0 ??? 07007+1.73 note: if possible, the error should be within 1%. osc b = 64 2 2n (n + 1) 10 6 osc 10 6 n = 64 2 2n b - 1 n: brr value (0 n 255) osc: crystal oscillator frequency in mhz b: baud rate (bits/second) n: internal clock source (0, 1, 2, or 3) the meaning of n is given by the table below: n cks1 cks0 clock 000 f 101 f /4 210 f /16 311 f /64 rev. 3.0, 09/98, page 203 of 361 table 10.4 examples of brr settings in synchronous mode xtal frequency (mhz) 2 4 8 10 16 20 bit rate nnnnnnnnnnnn 100 ???????????? 250 1 249 2 124 2 249 ?? 3 124 ?? 500 1 124 1 249 2 124 ?? 2 249 ?? 1k 0 249 1 124 1 249 ?? 2 124 ?? 2.5k 0 99 0 199 1 99 1 124 1 199 1 249 5k 0 49 0 99 0 199 0 249 1 99 1 124 10k 0 24 0 49 0 99 0 124 0 199 0 249 25k09019039049079099 50k0409019024039049 100k ?? 0409 ?? 019024 250k 0 0 * 0103040709 500k 0 0 * 01 ?? 0304 1m 0 0 * ?? 01 ?? 2.5m 00 * notes: blank: no setting is available. ? : a setting is available, but the bit rate is inaccurate. * : continuous transfer is not possible. b = osc 10 6 /[8 2 2n (n + 1)] n: brr value (0 n 255) osc: crystal oscillator frequency in mhz b: baud rate (bits per second) n: internal clock source (0, 1, 2, or 3) the meaning of n is given by the table below: n cks1 cks0 clock 000 f 101 f /4 210 f /16 311 f /64 rev. 3.0, 09/98, page 204 of 361 10.2.9 serial/timer control register (stcr) ? h'ffc3 bit:76543210 ????? mpe icks1 icks0 initial value: 1 1 1 1 1 0 0 0 read/write: ????? r/w r/w r/w the stcr is an 8-bit readable/writable register that controls the operating mode of the serial communication interface and selects input clock sources for the 8-bit timer counters (tcnt). the stcr is initialized to h'f8 by a reset. bits 7 to 3 ? reserved: these bits cannot be modified and are always read as 1. bit 2 ? multiprocessor enable (mpe): enables or disables the multiprocessor communication function on channels sci0 and sci1. bit 2 mpe description 0 the multiprocessor communication function is disabled, (initial value) regardless of the setting of the mp bit in smr. 1 the multiprocessor communication function is enabled. the multi- processor format can be selected by setting the mp bit in smr to 1. bits 1 and 0 ? internal clock source select 1 and 0 (icks1, icks0): these bits select the clock input to the timer counters (tcnt) in the 8-bit timers. for further information see section 7, 8-bit timers. rev. 3.0, 09/98, page 205 of 361 10.3 operation 10.3.1 overview the sci supports serial data transfer in two modes. in asynchronous mode each character is synchronized individually. in synchronous mode communication is synchronized with a clock signal. the selection of asynchronous or synchronous mode and the communication format depend on settings in the smr as indicated in table 10.5. the clock source depends on the settings of the c/ a bit in the smr and the cke1 and cke0 bits in the scr as indicated in table 10.6. (1) asynchronous mode: data lengths of seven or eight bits can be selected. a parity bit or multiprocessor bit can be added, and stop bit lengths of one or two bits can be selected. these selections determine the communication format and character length. framing errors (fer), parity errors (per) and overrun errors (orer) can be detected in receive data, and the line-break condition can be detected. an internal or external clock source can be selected for the serial clock. when an internal clock source is selected, the sci is clocked by the on-chip baud rate generator and can output a clock signal at the bit-rate frequency. when the external clock source is selected, the on-chip baud rate generator is not used. the external clock frequency must be 16 times the bit rate. (2) synchronous mode: the transmit data length is eight bits. overrun errors (orer) can be detected in receive data. an internal or external clock source can be selected for the serial clock. when an internal clock source is selected, the sci is clocked by the on-chip baud rate generator and outputs a serial clock signal. when the external clock source is selected, the on-chip baud rate generator is not used and the sci operates on the input serial clock. rev. 3.0, 09/98, page 206 of 361 table 10.5 communication formats used by sci smr settings communication format bit 7 c/a bit 6 chr bit 2 mp bit 5 pe bit 3 stop mode data length multipro- cessor bit parity bit stop-bit length 00000asynchr onous mode 8 bits none none 1 bit 1 2 bits 1 0 present 1 bit 1 2 bits 1 0 0 7 bits none 1 bit 1 2 bits 1 0 present 1 bit 1 2 bits 01 ? 0 8 bits present none 1 bit 1 2 bits 1 0 7 bits 1 bit 1 asynchronous mode (multiprocessor format) 2 bits 1 ???? synchronous mode 8 bits none none table 10.6 sci clock source selection smr scr serial transmit/receive clock bit 7 c/a bit 1 cke1 bit 0 cke0 mode clock source sck pin function 0 0 0 async internal input/output port (not used by sci) 1 serial clock output at bit rate 1 0 external serial clock input at 16 bit rate 1 1 0 0 sync internal serial clock output 1 1 0 external serial clock input 1 rev. 3.0, 09/98, page 207 of 361 10.3.2 asynchronous mode in asynchronous mode, each transmitted or received character is individually synchronized by framing it with a start bit and stop bit. full duplex data transfer is possible because the sci has independent transmit and receive sections. double buffering in both sections enables the sci to be programmed for continuous data transfer. figure 10.2 shows the general format of one character sent or received in asynchronous mode. the communication channel is normally held in the mark state (high). character transmission or reception starts with a transition to the space state (low). the first bit transmitted or received is the start bit (low). it is followed by the data bits, in which the least significant bit (lsb) comes first. the data bits are followed by the parity or multiprocessor bit, if present, then the stop bit or bits (high) confirming the end of the frame. in receiving, the sci synchronizes on the falling edge of the start bit, and samples each bit at the center of the bit (at the 8th cycle of the internal serial clock, which runs at 16 times the bit rate). 0 0 d0 d1 d2 d3 d4 one unit of data (one character or frame) 7 or 8 bits 1 bit 0 or 1 bit 1 or 2 bits start bit parity or multipro- cessor bit stop bit idle state (mark) d5 d6 d7 (lsb) (msb) 0/1 1 1 1 figure 10.2 data format in asynchronous mode (1) data format: table 10.7 lists the data formats that can be sent and received in asynchronous mode. twelve formats can be selected by bits in the smr. rev. 3.0, 09/98, page 208 of 361 table 10.7 data formats in asynchronous mode chr 0 0 0 0 1 1 1 1 0 0 1 1 pe 0 0 1 1 0 0 1 1 mp 0 0 0 0 0 0 0 0 1 1 1 1 stop 0 1 0 1 0 1 0 1 0 1 0 1 smr bits 123456789101112 s s s s s s s s s s s s 8-bit data stop 8-bit data stop stop 8-bit data p stop 8-bit data p stop stop 7-bit data stop 7-bit data stop stop 7-bit data p stop 7-bit data p stop stop 8-bit data mpb stop 8-bit data mpb stop stop 7-bit data mpb stop 7-bit data mpb stop stop notes: smr: serial mode register s: start bit stop: stop bit p: parity bit mpb: multiprocessor bit (2) clock: in asynchronous mode it is possible to select either an internal clock created by the on-chip baud rate generator, or an external clock input at the sck pin. the selection is made by the c/ a bit in the serial mode register (smr) and the cke1 and cke0 bits in the serial control register (scr). refer to table 10.7. if an external clock is input at the sck pin, its frequency should be 16 times the desired bit rate. if the internal clock provided by the on-chip baud rate generator is selected and the sck pin is used for clock output, the output clock frequency is equal to the bit rate, and the clock pulse rises at the center of the transmit data bits. figure 10.3 shows the phase relationship between the output clock and transmit data. 0 d0 d1 d2 d3 d4 one frame d5 d6 d7 0/1 1 1 figure 10.3 phase relationship between clock output and transmit data (asynchronous mode) rev. 3.0, 09/98, page 209 of 361 (3) transmitting and receiving data sci initialization: before transmitting or receiving, software must clear the te and re bits to 0 in the serial control register (scr), then initialize the sci as follows. note: when changing the communication mode or format, always clear the te and re bits to 0 before following the procedure given below. clearing te to 0 sets tdre to 1 and initializes the transmit shift register (tsr). clearing re to 0, however, does not initialize the rdrf, per, fer, and orer flags and receive data register (rdr), which retain their previous contents. when an external clock is used, the clock should not be stopped during initialization or subsequent operation. sci operation becomes unreliable if the clock is stopped. clear te and re bits to "0" in scr 1 bit interval elapsed? start transmitting or receiving no yes 1. select the communication format in the serial mode register (smr). 2. write the value corresponding to the bit rate in the bit rate register (brr). this step is not necessary when an external clock is used. 3. select interrupts and the clock source in the serial control register (scr). leave te and re cleared to "0." if clock output is selected, in asynchronous mode, clock output starts immediately after the setting is made in scr. 4. wait for at least the interval required to transmit or receive one bit, then set te or re in the serial control register (scr). setting te or re enables the sci to use the txd or rxd pin. also set the rie, tie, teie, and mpie bits as necessary to enable interrupts. the initial states are the mark transmit state, and the idle receive state (waiting for a start bit). select communication format in smr 1 set value in brr 2 set cke1 and cke0 bits in scr (leaving te and re cleared to "0") 3 set te or re to "1" in scr, and set rie, tie, teie, and mpie as necessary 4 initialization figure 10.4 sample flowchart for sci initialization rev. 3.0, 09/98, page 210 of 361 transmitting serial data: follow the procedure below for transmitting serial data. start transmitting read tdre bit in ssr tdre = "1"? write transmit data in tdr if using multiprocessor format, select mpbt value in ssr end of transmission? end 1 2 3 no yes no yes sci initialization: the transmit data output function of the txd pin is selected automatically. (a) (b) to continue transmitting serial data: read the tdre bit to check whether it is safe to write; if tdre = "1," write data in tdr, then clear tdre to "0." to end serial transmission: end of transmission can be confirmed by checking transition of the tend bit from "0" to "1." this can be reported by a tei interrupt. to output a break signal at the end of serial transmission: set the ddr bit to "1" and clear the dr bit to "0" (ddr and dr are i/o port registers), then clear te to "0" in scr. clear tdre bit to "0" in ssr read tend bit in ssr tend = "1"? no yes output break signal? no yes clear te bit in scr to "0" 4 sci status check and transmit data write: read the serial status register (ssr), check that the tdre bit is "1," then write transmit data in the transmit data register (tdr) and clear tdre to "0." if a multiprocessor format is selected, after writing the transmit data write "0" or "1" in the multiprocessor bit transfer (mpbt) in ssr. transition of the tdre bit from "0" to "1" can be reported by an interrupt. 1. 3. 4. 2. initialize set dr = "0," ddr = "1" serial transmission figure 10.5 sample flowchart for transmitting serial data rev. 3.0, 09/98, page 211 of 361 in transmitting serial data, the sci operates as follows. 1. the sci monitors the tdre bit in ssr. when tdre is cleared to 0 the sci recognizes that the transmit data register (tdr) contains new data, and loads this data from tdr into the transmit shift register (tsr). 2. after loading the data from tdr into tsr, the sci sets the tdre bit to 1 and starts transmitting. if the tie bit (tdr-empty interrupt enable) is set to 1 in scr, the sci requests a txi interrupt (tdr-empty interrupt) at this time. serial transmit data are transmitted in the following order from the txd pin: (a) start bit: one 0 bit is output. (b) transmit data: seven or eight bits are output, lsb first. (c) parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit is output. formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. (d) stop bit: one or two 1 bits (stop bits) are output. (e) mark state: output of 1 bits continues until the start bit of the next transmit data. 3. the sci checks the tdre bit when it outputs the stop bit. if tdre is 0, the sci loads new data from tdr into tsr, outputs the stop bit, then begins serial transmission of the next frame. if tdre is 1, the sci sets the tend bit to 1 in ssr, outputs the stop bit, then continues output of 1 bits in the mark state. if the teie bit (tsr-empty interrupt enable) in scr is set to 1, a tei interrupt (tsr-empty interrupt) is requested. figure 10.6 shows an example of sci transmit operation in asynchronous mode. "1" start bit "0" d0 d1 d7 0/1 stop bit "1" data parity bit stop bit data parity bit start bit "0" d0 d1 d7 0/1 "1" "1" mark (idle) state tdre tend txi request txi interrupt handler writes data in tdr and clears tdre to "0" txi request 1 frame tei request figure 10.6 example of sci transmit operation (8-bit data with parity and one stop bit) rev. 3.0, 09/98, page 212 of 361 receiving serial data: follow the procedure below for receiving serial data. start receiving read rdrf bit in ssr rdrf = "1"? read receive data from rdr, and clear rdrf bit to "0" in ssr per rer orer= "1"? clear re to "0" in scr finished receiving? end error handling start error handling fer = "1"? clear error flags to "0" in scr return break? clear re to "0" in scr end 1 2 no yes yes no no yes 4 1. 2. 3. 4. sci initialization: the receive data function of the rxd pin is selected automatically. sci status check and receive data read: read the serial status register (ssr), check that rdrf is set to "1," then read receive data from the receive data register (rdr) and clear rdrf to "0." transition of the rdrf bit from "0" to "1" can be reported by an rxi interrupt. to continue receiving serial data: read rdr and clear rdrf to "0" before the stop bit of the current frame is received. receive error handling and break detection: if a receive error occurs, read the orer, per, and fer bits in ssr to identify the error. after executing the necessary error handling, clear orer, per, and fer all to "0." transmitting and receiving cannot resume if orer, per, or fer remains set to "1." when a framing error occurs, the rxd pin can be read to detect the break state. yes no yes no read orer, per, and fer in ssr 3 initialize ^ ^ figure 10.7 sample flowchart for receiving serial data rev. 3.0, 09/98, page 213 of 361 in receiving, the sci operates as follows. 1. the sci monitors the receive data line and synchronizes internally when it detects a start bit. 2. receive data are shifted into rsr in order from lsb to msb. 3. the parity bit and stop bit are received. after receiving these bits, the sci makes the following checks: (a) parity check: the number of 1s in the receive data must match the even or odd parity setting of the o/ e bit in smr. (b) stop bit check: the stop bit value must be 1. if there are two stop bits, only the first stop bit is checked. (c) status check: rdrf must be 0 so that receive data can be loaded from rsr into rdr. if these checks all pass, the sci sets rdrf to 1 and stores the received data in rdr. if one of the checks fails (receive error), the sci operates as indicated in table 10.8. note: when a receive error flag is set, further receiving is disabled. the rdrf bit is not set to 1. be sure to clear the error flags. 4. after setting rdrf to 1, if the rie bit (receive-end interrupt enable) is set to 1 in scr, the sci requests an rxi (receive-end) interrupt. if one of the error flags (orer, per, or fer) is set to 1 and the rie bit in scr is also set to 1, the sci requests an eri (receive- error) interrupt. figure 10.8 shows an example of sci receive operation in asynchronous mode. table 10.8 receive error conditions and sci operation receive error abbreviation condition data transfer overrun error orer receiving of next data ends while rdrf is still set to 1 in ssr receive data not loaded from rsr into rdr framing error fer stop bit is 0 receive data loaded from rsr into rdr parity error per parity of receive data differs from even/odd parity setting in smr receive data loaded from rsr into rdr rev. 3.0, 09/98, page 214 of 361 "1" start bit "0" d0 d1 d7 0/1 stop bit "1" data parity bit start bit "0" d0 d1 d7 0/1 stop bit "0" data parity bit "1" mark (idle) state rdrf fer rxi request 1 frame framing error, eri request rxi interrupt handler reads data in rdr and clears rdrf to "0" figure 10.8 example of sci receive operation (8-bit data with parity and one stop bit) (4) multiprocessor communication the multiprocessor communication function enables several processors to share a single serial communication line. the processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). in multiprocessor communication, each receiving processor is addressed by an id. a serial communication cycle consists of two cycles: an id-sending cycle that identifies the receiving processor, and a data-sending cycle. the multiprocessor bit distinguishes id-sending cycles from data-sending cycles. the transmitting processor starts by sending the id of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. after receiving data with the multiprocessor bit set to 1, the receiving processor with an id matching the received data continues to receive further incoming data. multiple processors can send and receive data in this way. four formats are available. parity-bit settings are ignored when a multiprocessor format is selected. for details see table 10.7. rev. 3.0, 09/98, page 215 of 361 transmitting processor receiving processor a receiving processor b receiving processor c receiving processor d serial communication line (id = 01) (id = 02) (id = 03) (id = 04) serial data h'01 h'aa (mpb = 1) (mpb = 0) id-sending cycle: receiving processor address data-sending cycle: data sent to receiving processor specified by id mpb: multiprocessor bit figure 10.9 example of communication among processors using multiprocessor format (sending data h'aa to receiving processor a) transmitting multiprocessor serial data: see figures 10.5 and 10.6. receiving multiprocessor serial data: follow the procedure below for receiving multiprocessor serial data. rev. 3.0, 09/98, page 216 of 361 start receiving set mpie bit to "1" in scr read rdrf bit in ssr rdrf = "1"? read receive data from rdr own id? read orer and fer bits in ssr fer v orer = "1"? read rdrf bit in ssr rdrf = "1"? read orer and fer bits in ssr read receive data from rdr fer orer = "1"? finished receiving? clear re to "0" in scr end error handling fer = "1"? clear error flags return break? clear re bit to "0" in scr end 1 2 3 4 no yes no yes yes no no yes yes no no yes 5 1. 2. 3. 4. 5. sci initialization: the receive data function of the rxd pin is selected automatically. id receive cycle: set the mpie bit in the serial control register (scr) to "1." sci status check and id check: read the serial status register (ssr), check that rdrf is set to "1," then read receive data from the receive data register (rdr) and compare with the processor's own id. transition of the rdrf bit from "0" to "1" can be reported by an rxi interrupt. if the id does not match the receive data, set mpie to "1" again and clear rdrf to "0." if the id matches the receive data, clear rdrf to "0." sci status check and data receiving: read ssr, check that rdrf is set to "1," then read data from the receive data register (rdr) and write "0" in the rdrf bit. transition of the rdrf bit from "0" to "1" can be reported by an rxi interrupt. receive error handling and break detection: if a receive error occurs, read the orer and fer bits in ssr to identify the error. after executing the necessary error handling, clear both orer and fer to "0." receiving cannot resume while orer or fer remains set to "1." when a framing error occurs, the rxd pin can be read to detect the break state. yes no yes no initialize start error handling figure 10.10 sample flowchart for receiving multiprocessor serial data rev. 3.0, 09/98, page 217 of 361 figure 10.11 shows an example of sci receive operation using a multiprocessor format. "1" start bit "0" d0 d1 d7 "1" stop bit "1" data (id1) mpb start bit "0" d0 d1 d7 "0" stop bit "1" data (data1) mpb "1" mark (idle) state mpie rdrf rdr value id1 mpb detection, mpie = "0" rxi request rxi handler reads rdr data and clears rdrf to "0" not own id, so mpie is set to "1" again no rxi request, rdr not updated (multiprocessor interrupt) (a) own id does not match data "1" start bit "0" d0 d1 d7 "1" stop bit "1" data (id2) mpb start bit "0" d0 d1 d7 "0" stop bit "1" data (data2) mpb "1" mark (idle) state mpie rdrf rdr value id2 mpb detection, mpie = "0" rxi request rxi handler reads rdr data and clears rdrf to "0" own id, so receiving continues, with data received at each rxi mpie set to "1" again (multiprocessor interrupt) (a) own id does not match data id1 data 2 figure 10.11 example of sci receive operation (eight-bit data with multiprocessor bit and one stop bit) rev. 3.0, 09/98, page 218 of 361 10.3.3 synchronous mode (1) overview: in clocked synchronous mode, the sci transmits and receives data in synchronization with clock pulses. this mode is suitable for high-speed serial communication. the sci transmitter and receiver share the same clock but are otherwise independent, so full duplex communication is possible. the transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. figure 10.12 shows the general format in clocked synchronous serial communication. serial clock serial data bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb msb don't care don't care one unit (character or frame) of serial data * * note: * high except in continuous transmitting or receiving figure 10.12 data format in clocked synchronous communication in clocked synchronous serial communication, each data bit is sent on the communication line from one falling edge of the serial clock to the next. data are received in synchronization with the rising edge of the serial clock. in each character, the serial data bits are transmitted in order from lsb (first) to msb (last). after output of the msb, the communication line remains in the state of the msb. communication format: the data length is fixed at eight bits. no parity bit or multiprocessor bit can be added. clock: an internal clock generated by the on-chip baud rate generator or an external clock input from the sck pin can be selected by clearing or setting the cke1 bit in the serial control register (scr). see table 10.6. when the sci operates on an internal clock, it outputs the clock signal at the sck pin. eight clock pulses are output per transmitted or received character. when the sci is not transmitting or receiving, the clock signal remains at the high level. rev. 3.0, 09/98, page 219 of 361 (2) transmitting and receiving data sci initialization: the sci must be initialized in the same way as in asynchronous mode. see figure 10.4. when switching from asynchronous mode to clocked synchronous mode, check that the orer, fer, and per bits are cleared to 0. transmitting and receiving cannot begin if orer, fer, or per is set to 1. transmitting serial data: follow the procedure below for transmitting serial data. start transmitting read tdre bit in ssr tdre = "1"? write transmit data in tdr and clear tdre bit to "0" in ssr end of transmission? end 1 2 3 no yes no yes sci initialization: the transmit data output function of the txd pin is selected automatically. sci status check and transmit data write: read the serial status register (ssr), check that the tdre bit is "1," then write transmit data in the transmit data register (tdr) and clear tdre to "0." transition of the tdre bit from "0" to "1" can be reported by a txi interrupt. to continue transmitting serial data: read the tdre bit to check whether it is safe to write; if tdre = "1," write data in tdr, then clear tdre to "0." to end serial transmission: end of transmission can be confirmed by checking transition of the tend bit from "0" to "1." this can be reported by a tei interrupt. (a) (b) read tend bit in ssr tend = "1"? no yes 1. 2. 3. initialize clear te bit to "0" in scr serial transmission figure 10.13 sample flowchart for serial transmitting in transmitting serial data, the sci operates as follows. 1. the sci monitors the tdre bit in ssr. when tdre is cleared to 0 the sci recognizes that the transmit data register (tdr) contains new data, and loads this data from tdr into the transmit shift register (tsr). rev. 3.0, 09/98, page 220 of 361 2. after loading the data from tdr into tsr, the sci sets the tdre bit to 1 and starts transmitting. if the tie bit (tdr-empty interrupt enable) in scr is set to 1, the sci requests a txi interrupt (tdr-empty interrupt) at this time. if clock output is selected the sci outputs eight serial clock pulses, triggered by the clearing of the tdre bit to 0. if an external clock source is selected, the sci outputs data in synchronization with the input clock. data are output from the txd pin in order from lsb (bit 0) to msb (bit 7). 3. the sci checks the tdre bit when it outputs the msb (bit 7). if tdre is 0, the sci loads data from tdr into tsr, then begins serial transmission of the next frame. if tdre is 1, the sci sets the tend bit in ssr to 1, transmits the msb, then holds the output in the msb state. if the teie bit (transmit-end interrupt enable) in scr is set to 1, a tei interrupt (tsr-empty interrupt) is requested at this time. 4. after the end of serial transmission, the sck pin is held at the high level. figure 10.14 shows an example of sci transmit operation. serial clock serial data bit 0 bit 1 bit 7 bit 0 bit 1 bit 6 bit 7 txi request tdre tend txi interrupt handler writes data in tdr and clears tdre to "0" txi request txi request 1 frame figure 10.14 example of sci transmit operation receiving serial data: follow the procedure below for receiving serial data. when switching from asynchronous mode to clocked synchronous mode, be sure to check that per and fer are cleared to 0. if per or fer is set to 1 the rdrf bit will not be set and both transmitting and receiving will be disabled. rev. 3.0, 09/98, page 221 of 361 start receiving read rdrf bit in ssr rdrf = "1"? read receive data from rdr, and clear rdrf bit to "0" in ssr orer = "1"? read orer in ssr finished receiving? clear re to "0" in scr end error handling 1 2 3 no yes yes no no yes 4 1. 2. 3. 4. sci initialization: the receive data function of the rxd pin is selected automatically. sci status check and receive data read: read the serial status register (ssr), check that rdrf is set to "1," then read receive data from the receive data register (rdr) and clear rdrf to "0." transition of the rdrf bit from "0" to "1" can be reported by an rxi interrupt. to continue receiving serial data: read rdr and clear rdrf to "0" before the msb (bit 7) of the current frame is received. receive error handling: if a receive error occurs, read the orer bit in ssr then, after executing the necessary error handling, clear orer to "0." neither transmitting nor receiving can resume while orer remains set to "1." when clock output mode is selected, receiving can be halted temporarily by receiving one dummy byte and causing an overrun error. when preparations to receive the next data are completed, clear the orer bit to "0." this causes receiving to resume, so return to the step marked 2 in the flowchart. clear orer to "0" in ssr return overrun error handling start error handling initialize figure 10.15 sample flowchart for serial receiving in receiving, the sci operates as follows. 1. if an external clock is selected, data are input in synchronization with the input clock. if clock output is selected, as soon as the re bit is set to 1 the sci begins outputting the serial clock and inputting data. if clock output is stopped because the orer bit is set to 1, output of the serial clock and input of data resume as soon as the orer bit is cleared to 0. 2. receive data are shifted into rsr in order from lsb to msb. rev. 3.0, 09/98, page 222 of 361 after receiving the data, the sci checks that rdrf is 0 so that receive data can be loaded from rsr into rdr. if this check passes, the sci sets rdrf to 1 and stores the received data in rdr. if the check does not pass (receive error), the sci operates as indicated in table 10.8. note: both transmitting and receiving are disabled while a receive error flag is set. the rdrf bit is not set to 1. be sure to clear the error flag. 3. after setting rdrf to 1, if the rie bit (receive-end interrupt enable) is set to 1 in scr, the sci requests an rxi (receive-end) interrupt. if the orer bit is set to 1 and the rie bit in scr is set to 1, the sci requests an eri (receive-error) interrupt. when clock output mode is selected, clock output stops when the re bit is cleared to 0 or the orer bit is set to 1. to prevent clock count errors, it is safest to receive one dummy byte and generate an overrun error. figure 10.16 shows an example of sci receive operation. serial clock serial data bit 0 bit 1 bit 7 bit 0 bit 1 bit 6 bit 7 rxi request rdrf orer rxi interrupt handler reads data in rdr and clears rdrf to "0" rxi request overrun error, eri request 1 frame figure 10.16 example of sci receive operation transmitting and receiving serial data simultaneously: follow the procedure below for transmitting and receiving serial data simultaneously. if clock output mode is selected, output of the serial clock begins simultaneously with serial transmission. rev. 3.0, 09/98, page 223 of 361 start read tdre bit in ssr tdre = "1"? write transmit data in tdr and clear tdre bit to "0" in ssr rdrf = "1"? read rdrf bit in ssr end of transmitting and receiv- ing? clear te and re bits to "0" in scr end error handling 1 2 3 no yes yes no no yes 5 1. 2. 3. 4. 5. sci initialization: the transmit data output function of the txd pin and receive data input function of the rxd pin are selected, enabling simultaneous transmitting and receiving. sci status check and transmit data write: read the serial status register (ssr), check that the tdre bit is "1," then write transmit data in the transmit data register (tdr) and clear tdre to "0." transition of the tdre bit from "0" to "1" can be reported by a txi interrupt. sci status check and receive data read: read the serial status register (ssr), check that the rdrf bit is "1," then read receive data from the receive data register (rdr) and clear rdrf to "0." transition of the rdrf bit from "0" to "1" can be reported by an rxi interrupt. to continue transmitting and receiving serial data: read rdr and clear rdrf to "0" before the msb (bit 7) of the current frame is received. also read the tdre bit and check that it is set to "1," indicating that it is safe to write; then write data in tdr and clear tdre to "0" before the msb (bit 7) of the current frame is transmitted. receive error handling: if a receive error occurs, read the orer bit in ssr then, after executing the necessary error handling, clear orer to "0." neither transmitting nor receiving can resume while orer remains set to "1." rdrf= "1"? read receive data from rdr and clear rdrf bit to "0" in ssr read rdrf bit in ssr 4 no yes initialize figure 10.17 sample flowchart for serial transmitting and receiving note: in switching from transmitting or receiving to simultaneous transmitting and receiving, clear both te and re to 0, then set both te and re to 1. rev. 3.0, 09/98, page 224 of 361 10.4 interrupts the sci can request four types of interrupts: eri, rxi, txi, and tei. table 10.9 indicates the source and priority of these interrupts. the interrupt sources can be enabled or disabled by the tie, rie, and teie bits in the scr. independent signals are sent to the interrupt controller for each interrupt source, except that the receive-error interrupt (eri) is the logical or of three sources: overrun error, framing error, and parity error. the txi interrupt indicates that the next transmit data can be written. the tei interrupt indicates that the sci has stopped transmitting data. table 10.9 sci interrupt sources interrupt description priority eri receive-error interrupt (orer, fer, or per) high rxi receive-end interrupt (rdrf) txi tdr-empty interrupt (tdre) tei tsr-empty interrupt (tend) low 10.5 application notes application programmers should note the following features of the sci. (1) tdr write: the tdre bit in the ssr is simply a flag that indicates that the tdr contents have been transferred to the tsr. the tdr contents can be rewritten regardless of the tdre value. if a new byte is written in the tdr while the tdre bit is 0, before the old tdr contents have been moved into the tsr, the old byte will be lost. software should check that the tdre bit is set to 1 before writing to the tdr. (2) multiple receive errors: table 10.10 lists the values of flag bits in the ssr when multiple receive errors occur, and indicates whether the rsr contents are transferred to the rdr. rev. 3.0, 09/98, page 225 of 361 table 10.10 ssr bit states and data transfer when multiple receive errors occur ssr bits receive error rdrf orer fer per rsr ? rdr * 2 overrun error 1 * 1 100no framing error 0 0 1 0 yes parity error 0 0 0 1 yes overrun and framing errors 1 * 1 110no overrun and parity errors 1 * 1 101no framing and parity errors 0 0 1 1 yes overrun, framing, and parity errors 1 * 1 111no notes: 1. set to 1 before the overrun error occurs. 2. yes: the rsr contents are transferred to the rdr. no: the rsr contents are not transferred to the rdr. (3) line break detection: when the rxd pin receives a continuous stream of 0s in asynchronous mode (line-break state), a framing error occurs because the sci detects a 0 stop bit. the value h'00 is transferred from the rsr to the rdr. software can detect the line-break state as a framing error accompanied by h'00 data in the rdr. the sci continues to receive data, so if the fer bit is cleared to 0 another framing error will occur. (4) sampling timing and receive margin in asynchronous mode: the serial clock used by the sci in asynchronous mode runs at 16 times the baud rate. the falling edge of the start bit is detected by sampling the rxd input on the falling edge of this clock. after the start bit is detected, each bit of receive data in the frame (including the start bit, parity bit, and stop bit or bits) is sampled on the rising edge of the serial clock pulse at the center of the bit. see figure 10.18. it follows that the receive margin can be calculated as in equation (1). when the absolute frequency deviation of the clock signal is 0 and the clock duty factor is 0.5, data can theoretically be received with distortion up to the margin given by equation (2). this is a theoretical limit, however. in practice, system designers should allow a margin of 20% to 30%. rev. 3.0, 09/98, page 226 of 361 basic clock 0123456789101112131415161234567891011121314151612345 C7.5 pulses start bit +7.5 pulses d0 d1 receive data sync sampling data sampling figure 10.18 sampling timing (asynchronous mode) m = {(0.5 - 1/2n) - (d - 0.5)/n - (l - 0.5) f} 100 [%] (1) m: receive margin n: ratio of basic clock to baud rate (n=16) d: duty factor of clock-ratio of high pulse width to low width (0.5 to 1.0) l: frame length (9 to 12) f: absolute clock frequency deviation when d = 0.5 and f = 0 m = (0.5 - 1/2 16) 100 [%] = 46.875% (2) rev. 3.0, 09/98, page 227 of 361 section 11 a/d converter 11.1 overview the h8/338 series includes an analog-to-digital converter module with eight input channels. a/d conversion is performed by the successive approximations method with 8-bit resolution. 11.1.1 features the features of the on-chip a/d module are: 8-bit resolution eight analog input channels rapid conversion conversion time is 12.2s per channel (minimum) with a 10mhz system clock single and scan modes ? single mode: a/d conversion is performed once. ? scan mode: a/d conversion is performed in a repeated cycle on one to four channels. four 8-bit data registers these registers store a/d conversion results for up to four channels. sample-and-hold function external triggering can be selected a cpu interrupt (adi) can be requested at the completion of each a/d conversion cycle. rev. 3.0, 09/98, page 228 of 361 11.1.2 block diagram internal data bus adcr adcsr addra addrb addrc addrd legend: : a/d control register (8 bits) : a/d control/status register (8 bits) : a/d data register a (8 bits) : a/d data register b (8 bits) : a/d data register c (8 bits) : a/d data register d (8 bits) module data bus bus interface 8 bit d/a control circuit comparator sample and hold circuit av cc av ss an 0 + - an 1 an 2 an 3 an 4 an 5 an 6 ?/8 ?/16 adi interrupt signal an 7 adtrg a d c r a d c s r a d d r d a d d r c a d d r b a d d r a successive approximations register analog multi- plexer figure 11.1 block diagram of a/d converter rev. 3.0, 09/98, page 229 of 361 11.1.3 input pins table 11.1 lists the input pins used by the a/d converter module. the eight analog input pins are divided into two groups, consisting of analog inputs 0 to 3 (an 0 to an 3 ) and analog inputs 4 to 7 (an 4 to an 7 ), respectively. table 11.1 a/d input pins name abbreviation i/o function analog supply voltage av cc input power supply and reference voltage for the analog circuits. analog ground av ss input ground and reference voltage for the analog circuits. analog input 0 an 0 input analog input pins, group 0 analog input 1 an 1 input analog input 2 an 2 input analog input 3 an 3 input analog input 4 an 4 input analog input 5 an 5 input analog input pins, group 1 analog input 6 an 6 input analog input 7 an 7 input a/d external trigger adtrg input external trigger for starting a/d conversion 11.1.4 register configuration table 11.2 lists the registers of the a/d converter module. table 11.2 a/d registers name abbreviation r/w initial value address a/d data register a addra r h'00 h'ffe0 a/d data register b addrb r h'00 h'ffe2 a/d data register c addrc r h'00 h'ffe4 a/d data register d addrd r h'00 h'ffe6 a/d control/status register adcsr r/(w) * h'00 h'ffe8 a/d control register adcr r/w h'7e h'ffea note: software can write a 0 to clear bit 7, but cannot write a 1 in this bit. rev. 3.0, 09/98, page 230 of 361 11.2 register descriptions 11.2.1 a/d data registers (addr) ? h'ffe0 to h'ffe6 bit:76543210 addrn: initial value: 0 0 0 0 0 0 0 0 read/write: r r r r r r r r (n = a to d) the four a/d data registers (addra to addrd) are 8-bit read-only registers that store the results of a/d conversion. each data register is assigned to two analog input channels as indicated in table 11.3. the a/d data registers are always readable by the cpu. the a/d data registers are initialized to h'00 at a reset and in the standby modes. table 11.3 assignment of data registers to analog input channels analog input channel group 0 group 1 a/d data register an0 an4 addra an1 an5 addrb an2 an6 addrc an3 an7 addrd 11.2.2 a/d control/status register (adcsr) ? h'ffe8 bit:76543210 adf adie adst scan cks ch2 ch1 ch0 initial value: 0 0 0 0 0 0 0 0 read/write: r/(w) * r/w r/w r/w r/w r/w r/w r/w note: software can write a 0 in bit 7 to clear the flag, but cannot write a 1 in this bit. the a/d control/status register (adcsr) is an 8-bit readable/writable register that controls the operation of the a/d converter module. the adcsr is initialized to h'00 at a reset and in the standby modes. rev. 3.0, 09/98, page 231 of 361 bit 7 ? a/d end flag (adf): this status flag indicates the end of one cycle of a/d conversion. bit 7 adf description 0 to clear adf, the cpu must read adf after it has been set to 1, (initial value) then write a 0 in this bit. 1 this bit is set to 1 at the following times: (1) single mode: when one a/d conversion is completed. (2) scan mode: when inputs on all selected channels have been converted. bit 6 ? a/d interrupt enable (adie): this bit selects whether to request an a/d interrupt (adi) when a/d conversion is completed. bit 6 adie description 0 the a/d interrupt request (adi) is disabled. (initial value) 1 the a/d interrupt request (adi) is enabled. bit 5 ? a/d start (adst): the a/d converter operates while this bit is set to 1. this bit can be set to 1 by the external trigger signal adtrg . bit 5 adst description 0 a/d conversion is halted. (initial value) 1 (1) single mode: one a/d conversion is performed. the adst bit is automatically cleared to 0 at the end of the conversion. (2) scan mode: a/d conversion starts and continues cyclically on the selected channels until the adst bit is cleared to 0 by software (or a reset, or by entry to a standby mode). bit 4 ? scan mode (scan): this bit selects the scan mode or single mode of operation. see section 11.3, operation for descriptions of these modes. the mode should be changed only when the adst bit is cleared to 0. bit 4 scan description 0 single mode (initial value) 1 scan mode rev. 3.0, 09/98, page 232 of 361 bit 3 ? clock select (cks): this bit controls the a/d conversion time. the conversion time should be changed only when the adst bit is cleared to 0. bit 3 cks description 0 conversion time = 242 states (max) (initial value) 1 conversion time = 122 states (max) bits 2 to 0 ? channel select 2 to 0 (ch2 to ch0): these bits and the scan bit combine to select one or more analog input channels. the channel selection should be changed only when the adst bit is cleared to 0. channel select selected channels group select ch2 ch1 ch0 single mode scan mode 000an 0 (initial value) an 0 01an 1 an 0 , an 1 10an 2 an 0 to an 2 11an 3 an 0 to an 3 100an 4 an 4 01an 5 an 4 , an 5 10an 6 an 4 to an 6 11an 7 an 4 to an 7 rev. 3.0, 09/98, page 233 of 361 11.2.3 a/d control register (adcr) ? h'ffea bit:76543210 trge ?????? chs initial value: 0 1 1 1 1 1 1 0 read/write: r/w ?????? r/w the a/d control register (adcr) is an 8-bit readable/writable register that enables or disables the a/d external trigger signal. the adcr is initialized to h'7e at a reset and in the standby modes. bit 7 ? trigger enable (trge): this bit enables the adtrg (a/d external trigger) signal to set the adst bit and start a/d conversion. bit 7 trge description 0 a/d external trigger is disabled. adtrg does not set the adst bit. (initial value) 1 a/d external trigger is enabled. adtrg sets the adst bit. (the adst bit can also be set by software.) bits 6 to 1 ? reserved: these bits cannot be modified and are always read as 1. bit 0 ? channel set select (chs): this bit is reserved. it does not affect any operation in the h8/338 series. rev. 3.0, 09/98, page 234 of 361 11.3 operation the a/d converter performs 8 successive approximations to obtain a result ranging from h'00 (corresponding to av ss ) to h'ff (corresponding to av cc ). the a/d converter module can be programmed to operate in single mode or scan mode as explained below. 11.3.1 single mode (scan = 0) the single mode is suitable for obtaining a single data value from a single channel. a/d conversion starts when the adst bit is set to 1, either by software or by a high-to-low transition of the adtrg signal (if enabled). during the conversion process the adst bit remains set to 1. when conversion is completed, the adst bit is automatically cleared to 0. when the conversion is completed, the adf bit is set to 1. if the interrupt enable bit (adie) is also set to 1, an a/d conversion end interrupt (adi) is requested, so that the converted data can be processed by an interrupt-handling routine. the adf bit is cleared when software reads the a/d control/status register (adcsr), then writes a 0 in this bit. before selecting the single mode, clock, and analog input channel, software should clear the adst bit to 0 to make sure the a/d converter is stopped. changing the mode, clock, or channel selection while a/d conversion is in progress can lead to conversion errors. a/d conversion begins when the adst bit is set to 1 again. the same instruction can be used to alter the mode and channel selection and set adst to 1. the following example explains the a/d conversion process in single mode when channel 1 (an1) is selected and the external trigger is disabled. figure 11.2 shows the corresponding timing chart. (1) software clears the adst bit to 0, then selects the single mode (scan = 0) and channel 1 (ch2 to ch0 = 001), enables the a/d interrupt request (adie = 1), and sets the adst bit to 1 to start a/d conversion. coding example: (when using the slow clock, cks = 0) bclr #5, @h'ffe8 ;clear adst mov.b #h'7f, rol mov.b rol, @h'ffea ;disable external trigger mov.b #h'61, rol mov.b rol, @h'ffe8 ;select mode and channel and set adst to 1 rev. 3.0, 09/98, page 235 of 361 value set in adcsr adf adie adst scan cks ch2 ch1 ch0 01100001 (2) the a/d converter converts the voltage level at the an1 input pin to a digital value. at the end of the conversion process the a/d converter transfers the result to register addrb, sets the adf bit to 1, clears the adst bit to 0, and halts. (3) adf = 1 and adie = 1, so an a/d interrupt is requested. (4) the user-coded a/d interrupt-handling routine is started. (5) the interrupt-handling routine reads the adcsr value, then writes a 0 in the adf bit to clear this bit to 0. (6) the interrupt-handling routine reads and processes the a/d conversion result (addrb). (7) the routine ends. steps (2) to (7) can now be repeated by setting the adst bit to 1 again. rev. 3.0, 09/98, page 236 of 361 interrupt (adi) set* set* a/d conversion starts waiting waiting waiting waiting a/d conver- sion (1) a/d conver- sion (2) a/d conversion result (1) read result read result a/d conversion result (2) waiting waiting set* clear* clear* adie adst adf channel 0 (an 0 ) channel 1 (an 1 ) channel 2 (an 2 ) channel 3 (an 3 ) addra addrb addrc addrd note: * indicates execution of a software instruction figure 11.2 a/d operation in single mode (when channel 1 is selected) rev. 3.0, 09/98, page 237 of 361 11.3.2 scan mode (scan = 1) the scan mode can be used to monitor analog inputs on one or more channels. when the adst bit is set to 1, either by software or by a high-to-low transition of the adtrg signal (if enabled), a/d conversion starts from the first channel selected by the ch bits. when ch2 = 0 the first channel is an 0 . when ch2 = 1 the first channel is an 4 . if the scan group includes more than one channel (i.e., if bit ch1 or ch0 is set), conversion of the next channel (an 1 or an 5 ) begins as soon as conversion of the first channel ends. conversion of the selected channels continues cyclically until the adst bit is cleared to 0. the conversion results are placed in the data registers corresponding to the selected channels. the a/d data registers are readable by the cpu. before selecting the scan mode, clock, and analog input channels, software should clear the adst bit to 0 to make sure the a/d converter is stopped. changing the mode, clock, or channel selection while a/d conversion is in progress can lead to conversion errors. a/d conversion begins from the first selected channel when the adst bit is set to 1 again. the same instruction can be used to alter the mode and channel selection and set adst to 1. the following example explains the a/d conversion process when three channels in group 0 are selected (an 0 , an 1 , and an 2 ) and the external trigger is disabled. figure 11.3 shows the corresponding timing chart. (1) software clears the adst bit to 0, then selects the scan mode (scan = 1), scan group 0 (ch2 = 0), and analog input channels an 0 to an 2 (ch1 = 1 and ch0 = 0) and sets the adst bit to 1 to start a/d conversion. coding example: (with slow clock and adi interrupt enabled) bclr #5, @h'ffe8 ;clear adst mov.b #h'7f, rol mov.b rol, @h'ffea ;disable external trigger mov.b #h'72, rol mov.b rol, @h'ffe8 ;select mode and channels and set adst to 1 value set in adcsr adf adie adst scan cks ch2 ch1 ch0 01110010 (2) the a/d converter converts the voltage level at the an0 input pin to a digital value, and transfers the result to register addra. (3) next the a/d converter converts an1 and transfers the result to addrb. then it converts an2 and transfers the result to addrc. rev. 3.0, 09/98, page 238 of 361 (4) after all selected channels (an 0 to an 2 ) have been converted, the ad converter sets the adf bit to 1. if the adie bit is set to 1, an a/d interrupt (adi) is requested. then the a/d converter begins converting an0 again. (5) steps (2) to (4) are repeated cyclically as long as the adst bit remains set to 1. to stop the a/d converter, software must clear the adst bit to 0. regardless of which channel is being converted when the adst bit is cleared to 0, when the adst bit is set to 1 again, conversion begins from the the first selected channel (an 0 ). waiting waiting a/d conver- sion (4) waiting continuous a/d conversion a/d conver- sion (1) a/d conversion result (2) a/d conversion result (4) a/d conver- sion result (1) a/d conversion result (3) transfer waiting a/d conver- sion (3) waiting waiting set* clear*1 clear*1 adst adf channel 0 (an 0 ) channel 1 (an 1 ) channel 2 (an 2 ) channel 3 (an 3 ) addra addrb addrc addrd waiting a/d conver- sion (2) waiting a/d conver- sion (5) waiting * 2 notes: 1. indicates execution of a software instruction 2. data undergoing conversion when adst bit is cleared are ignored. a/d conversion time figure 11.3 a/d operation in scan mode (when channels 0 to 2 are selected) rev. 3.0, 09/98, page 239 of 361 11.3.3 input sampling time and a/d conversion time the a/d converter includes a built-in sample-and-hold circuit. sampling of the input starts at a time td after the adst bit is set to 1. the sampling process lasts for a time t spl . the actual a/d conversion begins after sampling is completed. figure 11.4 shows the timing of these steps. table 11.4 (a) lists the conversion times for the single mode. table 11.4 (b) lists the conversion times for the scan mode. the total conversion time (t conv ) includes td and t spl . the purpose of t d is to synchronize the adcsr write time with the a/d conversion process, so the length of t d is variable. the total conversion time therefore varies within the minimum to maximum ranges indicated in table 11.4 (a) and (b). in the scan mode, the ranges given in table 11.4 (b) apply to the first conversion. the length of the second and subsequent conversion processes is fixed at 256 states (when cks = 0) or 128 states (when cks = 1). rev. 3.0, 09/98, page 240 of 361 ? internal address bus write signal input sampling timing adf (2) t d t spl (1) (1) (2) t d t spl t conv legend: : adcsr write cycle : adcsr address : synchronization delay : input sampling time : total a/d conversion time t conv figure 11.4 a/d conversion timing table 11.4 (a) a/d conversion time (single mode) cks = 0 cks = 1 item symbol min typ max min typ max synchronization delay t d 18 ? 33 10 ? 17 input sampling time t spl ? 63 ?? 31 ? total a/d conversion time t conv 227 ? 242 115 ? 122 rev. 3.0, 09/98, page 241 of 361 table 11.4 (b) a/d conversion time (scan mode) cks = 0 cks = 1 item symbol min typ max min typ max synchronization delay t d 18 ? 33 10 ? 17 input sampling time t spl ? 63 ?? 31 ? total a/d conversion time t conv 259 ? 274 131 ? 138 note: values in the tables above are numbers of states. 11.3.4 external trigger input timing a/d conversion can be started by external trigger input at the adtrg pin. this input is enabled or disabled by the trge bit in the a/d control register (adcr). if the trge bit is set to 1, when a falling edge of adtrg is detected the adst bit is set to 1 and a/d conversion begins. subsequent operation in both single and scan modes is the same as when the adst bit is set to 1 by software. figure 11.5 shows the trigger timing. ? internal trigger signal adtrg adst a/d conversion figure 11.5 external trigger input timing rev. 3.0, 09/98, page 242 of 361 11.4 interrupts the a/d conversion module generates an a/d-end interrupt request (adi) at the end of a/d conversion. the adi interrupt request can be enabled or disabled by the adie bit in the a/d control/status register (adcsr). rev. 3.0, 09/98, page 243 of 361 section 12 d/a converter 12.1 overview the h8/338 series has an on-chip d/a converter module with two channels. 12.1.1 features features of the d/a converter module are listed below. eight-bit resolution two-channel output maximum conversion time: 10s (with 30pf load capacitance) output voltage: 0v to av cc rev. 3.0, 09/98, page 244 of 361 12.1.2 block diagram figure 12.1 shows a block diagram of the d/a converter. internal data bus dacr dadr0 dadr1 : d/a control register : d/a data register 0 : d/a data register 1 module data bus bus interface 8 bit d/a control circuit av cc da 0 da 1 av ss dadr0 dadr1 dacr legend: figure 12.1 d/a converter block diagram rev. 3.0, 09/98, page 245 of 361 12.1.3 input and output pins table 12.1 lists the input and output pins used by the d/a converter module. table 12.1 input and output pins of d/a converter module name abbreviation i/o function analog supply voltage av cc input power supply and reference voltage for analog circuits analog ground av ss input ground and reference voltage for analog circuits analog output 0 da 0 output analog output channel 0 analog output 1 da 1 output analog output channel 1 12.1.4 register configuration table 12.2 lists the three registers of the d/a converter module. table 12.2 d/a converter registers name abbreviation r/w initial value address d/a data register 0 dadr0 r/w h'00 h'ffa8 d/a data register 1 dadr1 r/w h'00 h'ffa9 d/a control register dacr r/w h'1f h'ffaa rev. 3.0, 09/98, page 246 of 361 12.2 register descriptions 12.2.1 d/a data registers 0 and 1 (dadr0, dadr1) h'ffa8, h'ffa9 bit:76543210 initial value: 0 0 0 0 0 0 0 0 read/write: r/w r/w r/w r/w r/w r/w r/w r/w d/a data registers 0 and 1 (dadr0 and dadr1) are 8-bit readable and writable registers that store data to be converted. when analog output is enabled, the value in the d/a data register is converted and output continuously at the analog output pin. the d/a data registers are initialized to h'00 at a reset and in the standby modes. 12.2.2 d/a control register (dacr) h'ffaa bit:76543210 daoe1 daoe0 dae ????? initial value: 0 0 0 1 1 1 1 1 read/write: r/w r/w r/w ????? the d/a control register is an 8-bit readable and writable register that controls the operation of the d/a converter module. the d/a control register is initialized to h'1f at a reset and in the standby modes. bit 7 ? d/a output enable 1 (daoe1): controls analog output from the d/a converter. bit 7 daoe1 description 0 analog output at da 1 is disabled. 1 d/a conversion is enabled on channel 1. analog output is enabled at da 1 . rev. 3.0, 09/98, page 247 of 361 bit 6 ? d/a output enable 0 (daoe0): controls analog output from the d/a converter. bit 6 daoe0 description 0 analog output at da 0 is disabled. 1 d/a conversion is enabled on channel 0. analog output is enabled at da 0 . bit 5 ? d/a enable (dae): controls analog output from the d/a converter, in combination with bits daoe0 and daoe1. d/a conversion is controlled independently on channels 0 and 1 when dae = 0. channels 0 and 1 are controlled together when dae = 1. whether or not to output the converted results is always controlled independently by daoe0 and daoe1. bit 7 daoe1 bit 6 daoe0 bit 5 dae d/a conversion 00 ? disabled on channels 0 and 1. 0 1 0 enabled on channel 0. disabled on channel 1. 0 1 1 enabled on channels 0 and 1. 1 0 0 disabled on channel 0. enabled on channel 1. 1 0 1 enabled on channels 0 and 1. 11 ? enabled on channels 0 and 1. when the dae bit is set to 1, analog power supply current drain is the same as during a/d and d/a conversion, even if the daoe0 and daoe1 bits in dacr and the adst bit in adscr are cleared to 0. bits 4 to 0 ? reserved: these bits cannot be modified and are always read as 1. rev. 3.0, 09/98, page 248 of 361 12.3 operation the d/a converter module has two built-in d/a converter circuits that can operate independently. d/a conversion is performed continuously whenever enabled by the d/a control register. when a new value is written in dadr0 or dadr1, conversion of the new value begins immediately. the converted result is output by setting the daoe0 or daoe1 bit to 1. an example of conversion on channel 0 is given next. figure 12.2 shows the timing. (1) software writes the data to be converted in dadr0. (2) d/a conversion begins when the daoe0 bit in dacr is set to 1. after a conversion delay, analog output appears at the da0 pin. the output value is avcc (dadr0 value)/256. this output continues until a new value is written in dadr0 or the daoe0 bit is cleared to 0. (3) if a new value is written in dadr0, conversion begins immediately. output of the converted result begins after the conversion delay time. (4) when the daoe0 bit is cleared to 0, da0 becomes an input pin. ? address dadr0 daoe0 da0 t dconv t dconv high-impedance state conversion data (1) conversion data (1) conversion data (2) conversion data (2) dadr0 write cycle t dconv legend: : d/a conversion time dadr write cycle dadr0 write cycle dadr write cycle figure 12.2 d/a conversion (example) rev. 3.0, 09/98, page 249 of 361 section 13 ram 13.1 overview the h8/338 includes 2k bytes of on-chip static ram. the h8/337 and h8/336 have 1k byte. the ram is connected to the cpu by a 16-bit data bus. both byte and word access to the on-chip ram are performed in two states, enabling rapid data transfer and instruction execution. the on-chip ram is assigned to addresses h'f780 to h'ff7f in the address space of the h8/338, and addresses h'fb80 to h'ff7f in the address space of the h8/337 and h8/336. the rame bit in the system control register (syscr) can enable or disable the on-chip ram, permitting these addresses to be allocated to external memory instead, if so desired. 13.2 block diagram figure 13.1 is a block diagram of the on-chip ram. internal data bus (upper 8 bits) internal data bus (lower 8 bits) even address odd address h'f780 h'f782 h'ff7e h'f781 h'f783 h'ff7f on-chip ram figure 13.1 block diagram of on-chip ram (h8/338) rev. 3.0, 09/98, page 250 of 361 13.3 ram enable bit (rame) in system control register (syscr) the on-chip ram is enabled or disabled by the rame (ram enable) bit in the system control register (syscr). bit:76543210 ssby sts2 sts1 sts0 ? nmieg dpme rame initial value: 0 0 0 0 1 0 0 1 read/write: r/w r/w r/w r/w ? r/w r/w r/w the only bit in the system control register that concerns the on-chip ram is the rame bit. see section 2.2, "system control register," for the other bits. bit 0 ? ram enable (rame): this bit enables or disables the on-chip ram. the rame bit is initialized to "1" on the rising edge of the res signal, so a reset enables the on- chip ram. the rame bit is not initialized in the software standby mode. bit 7 rame description 0 on-chip ram is disabled. 1 on-chip ram is enabled. (initial value) 13.4 operation 13.4.1 expanded modes (modes 1 and 2) if the rame bit is set to "1," accesses to addresses h'f780 to h'ff7f in the h8/338 and addresses h'fb80 to h'ff7f in the h8/337 and h8/336 are directed to the on-chip ram. if the rame bit is cleared to "0," accesses to these addresses are directed to the external data bus. 13.4.2 single-chip mode (mode 3) if the rame bit is set to "1," accesses to addresses h'f780 to h'ff7f in the h8/338 and addresses h'fb80 to h'ff7f in the h8/337 and h8/336 are directed to the on-chip ram. if the rame bit is cleared to "0," the on-chip ram data cannot be accessed. attempted write access has no effect. attempted read access always results in h'ff data being read. rev. 3.0, 09/98, page 251 of 361 section 14 rom 14.1 overview the h8/338 includes 48k bytes of high-speed, on-chip rom. the h8/337 has 32k bytes. the h8/336 has 24k bytes. the on-chip rom is connected to the cpu via a 16-bit data bus. both byte data and word data are accessed in two states, enabling rapid data transfer and instruction fetching. the on-chip rom is enabled or disabled depending on the mcu operating mode, which is determined by the inputs at the mode pins (md 1 and md 0 ). see table 14.1. table 14.1 on-chip rom usage in each mcu mode mode pins mode md 1 md 0 on-chip rom mode 1 (expanded mode) 0 1 disabled (external addresses) mode 2 (expanded mode) 1 0 enabled mode 3 (single-chip mode) 1 1 enabled the h8/338 and h8/337 are available with electrically programmable rom (prom), or with masked rom. the prom version has a prom mode in which the chip can be programmed with a standard prom writer. rev. 3.0, 09/98, page 252 of 361 14.1.1 block diagram figure 14.1 is a block diagram of the on-chip rom. internal data bus (upper 8 bits) internal data bus (lower 8 bits) even addresses odd addresses h'0000 h'0002 h'bffe h'0001 h'0003 h'bfff on-chip rom figure 14.1 block diagram of on-chip rom (h8/338) 14.2 prom mode (h8/338, h8/337) 14.2.1 prom mode setup in the prom mode of the prom version of the h8/338 and h8/337, the usual microcomputer functions are halted to allow the on-chip prom to be programmed. the programming method is the same as for the hn27c101. to select the prom mode, apply the signal inputs listed in table 14.2. table 14.2 selection of prom mode pin input mode pin md 1 low mode pin md 0 low stby pin low pins p6 3 and p6 4 high rev. 3.0, 09/98, page 253 of 361 14.2.2 socket adapter pin assignments and memory map the h8/338 and h8/337 can be programmed with a general-purpose prom writer by using a socket adapter to change the pin-out to 32 pins. there are different socket adapters for different packages as listed in table 14.3. the same socket adapters can be used for both the h8/338 and h8/337. figure 14.2 shows the socket adapter pin assignments. table 14.3 socket adapters package socket adapter 84-pin plcc hs338esc02h 84-pin windowed lcc hs338esg02h 80-pin qfp hs338esh02h the prom size is 48k bytes for the h8/338 and 32k bytes for the h8/337. figures 14.3 and 14.4 show memory maps of the h8/338 and h8/337 in prom mode. h'ff data should be specified for unused address areas in the on-chip prom. when programming with a prom writer, limit the program address range to h'0000 to h'bfff for the h8/338 and h'0000 to h'7fff for the h8/337. specify h'ff data for addresses h'c000 and above (h8/338) or h'8000 and above (h8/337). if these addresses are programmed by mistake, it may become impossible to program or verify the prom data. the same problem may occur if an attempt is made to program the chip in page programming mode. particular care is required with a plastic package, since the programmed data cannot be erased. rev. 3.0, 09/98, page 254 of 361 1 6 65 66 67 68 69 70 71 72 64 63 62 61 60 59 58 57 55 54 53 52 51 50 49 48 20 19 18 24 25 29 8 47 5 4 7 38 12 56 73 cg-84, cp-84 pin res nmi p3 p3 p3 p3 p3 p3 p3 p3 p1 p1 p1 p1 p1 p1 p1 p1 p2 p2 p2 p2 p2 p2 p2 p2 p9 p9 p9 p6 p6 av v v md md stby av v v v v v v v 12 17 79 80 81 82 83 84 1 3 78 77 76 75 74 73 72 71 69 68 67 66 65 63 62 61 32 31 30 36 37 42 19 60 16 15 18 51 2 4 23 24 41 64 70 pin v ea eo eo eo eo eo eo eo eo ea ea ea ea ea ea ea ea ea oe ea ea ea ea ea ce ea ea pgm v v hn27c101 (32 pins) 1 26 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 24 23 25 4 28 29 22 2 3 31 32 16 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 cc cc cc 0 1 ss ss ss ss ss ss ss ss 9 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 10 11 12 13 14 16 15 pp cc h8/337, h8/338 eprom socket note: all pins not listed in this figure should be left open. v : eo to eo ea to ea oe: ce: pgm: pp 0 7 0 16 : program voltage (12.5 v) : data input/output : address input : output enable : chip enable : program enable ss fp-80a figure 14.2 socket adapter pin assignments rev. 3.0, 09/98, page 255 of 361 on-chip prom undetermined output* address in mcu mode address in prom mode h'0000 h'0000 h'bfff h'1ffff h'bfff note: * if this address area is read in prom mode, the output data are undetermined. figure 14.3 h8/338 memory map in prom mode rev. 3.0, 09/98, page 256 of 361 on-chip prom undetermined output* address in mcu mode address in prom mode h'0000 h'0000 h'7fff h'1ffff h'7fff note: * if this address area is read in prom mode, the output data are undetermined. figure 14.4 h8/337 memory map in prom mode rev. 3.0, 09/98, page 257 of 361 14.3 programming the write, verify, and other sub-modes of the prom mode are selected as shown in table 14.4. table 14.4 selection of sub-modes in prom mode sub-mode ce oe pgm v pp v cc eo 7 to eo 0 ea 16 to ea 0 write low high low v pp v cc data input address input verify low low high v pp v cc data output address input programming inhibited low low high high low high low high low high low high v pp v cc high impedance address input note: the v pp and v cc pins must be held at the v pp and v cc voltage levels. the h8/338 or h8/337 prom has the same standard read/write specifications as the hn27c101 eprom. page programming is not supported, however, so do not select page programming mode. prom writers that provide only page programming cannot be used. when selecting a prom writer, check that it supports the byte-at-a-time high-speed programming mode. be sure to set the address range to h'0000 to h'bfff for the h8/338, and to h'0000 to h'7fff for the h8/337. 14.3.1 writing and verifying an efficient, high-speed programming procedure can be used to write and verify prom data. this procedure writes data quickly without subjecting the chip to voltage stress and without sacrificing data reliability. it leaves the data h'ff written in unused addresses. figure 14.5 shows the basic high-speed programming flowchart. tables 14.5 and 14.6 list the electrical characteristics of the chip in the prom mode. figure 14.6 shows a write/verify timing chart. rev. 3.0, 09/98, page 258 of 361 start set read mode vcc = 5.0v 0.25v, vpp = vcc set program/verify mode vcc = 6.0v 0.25v, vpp = 12.5v 0.3v address = 0 n = 1 n + 1 n program tpw = 0.2 ms 5% program topw = 0.2n ms address + 1 address verify ok? n < 25? last address? all addresses read? end error no no no yes yes yes go nogo figure 14.5 high-speed programming flowchart rev. 3.0, 09/98, page 259 of 361 table 14.5 dc characteristics (when v cc = 6.0v 0.25v, v pp = 12.5v 0.3v, v ss = 0v, ta = 25 c 5 c) item symbol min typ max unit measurement conditions input high voltage eo 7 - eo 0 , a 16 - a 0 , oe , ce , pgm v ih 2.4 ? v cc + 0.3 v input low voltage eo 7 - eo 0 , a 16 - a 0 , oe , ce , pgm v il - 0.3 ? 0.8 v output high voltage eo 7 - eo 0 v oh 2.4 ?? vi oh = - 200a output low voltage eo 7 - eo 0 v ol ?? 0.45 v i ol = 1.6ma input leakage current eo 7 - eo 0 , ea 16 - ea 0 , oe , ce , pgm |i li | ?? 2av in = 5.25v/ 0.5v v cc current i cc ?? 40 ma v pp current i pp ?? 40 ma table 14.6 ac characteristics (when v cc = 6.0v 0.25v, v pp = 12.5v 0.3v, ta = 25 c 5 c) item symbol min typ max unit measurement conditions address setup time t as 2 ?? s see figure 14.6 * oe setup time t oes 2 ?? s data setup time t ds 2 ?? s address hold time t ah 0 ?? s data hold time t dh 2 ?? s data output disable time t df ?? 130 ns v pp setup time t vps 2 ?? s program pulse width t pw 0.19 0.20 0.21 ms note: input pulse level: 0.8v to 2.2v input rise/fall time 20ns timing reference levels: input ? 1.0v, 2.0v; output ? 0.8v, 2.0v rev. 3.0, 09/98, page 260 of 361 table 14.6. ac characteristics (cont) (when v cc = 6.0v 0.25v, v pp = 12.5v 0.3v, ta = 25 c 5 c) item symbol min typ max unit measurement conditions oe pulse width for overwrite- programming t opw 0.19 ? 5.25 ms see figure 14.6 * v cc setup time t vcs 2 ?? s ce setup time t ces 2 ?? s data output delay time t oe 0 ? 150 ns note: input pulse level: 0.8v to 2.2v input rise/fall time 20ns timing reference levels: input ? 1.0v, 2.0v; output ? 0.8v, 2.0v address data v pp t as v pp v cc v cc + 1 v cc v cc ce pgm oe write t ds t dh t df t ah t pw t oe t oes t opw t vps t vcs t ces input data output data verify figure 14.6 prom write/verify timing rev. 3.0, 09/98, page 261 of 361 14.3.2 notes on writing (1) write with the specified voltages and timing. the programming voltage (v pp ) is 12.5v. caution: applied voltages in excess of the specified values can permanently destroy the chip. be particularly careful about the prom writers overshoot characteristics. if the prom writer is set to hn27c101 specifications, v pp will be 12.5v. (2) before writing data, check that the socket adapter and chip are correctly mounted in the prom writer. overcurrent damage to the chip can result if the index marks on the prom writer, socket adapter, and chip are not correctly aligned. (3) dont touch the socket adapter or chip while writing. touching either of these can cause contact faults and write errors. (4) page programming is not supported. do not select page programming mode. (5) the h8/338 prom size is 48k bytes. the h8/337 prom size is 32k bytes. set the address range to h'0000 to h'bfff for the h8/338, and to h'0000 to h'7fff for the h8/337. when programming, specify h'ff data for unused address areas (h'c000 to h'1ffff in the h8/338, h'8000 to h'1ffff in the h8/337). rev. 3.0, 09/98, page 262 of 361 14.3.3 reliability of written data an effective way to assure the data holding characteristics of the programmed chips is to bake them at 150 c, then screen them for data errors. this procedure quickly eliminates chips with prom memory cells prone to early failure. figure 14.7 shows the recommended screening procedure. install note: * baking time should be measured from the point when the baking oven reaches 150c. write and verify program read and check program v cc = 5.0v bake with power off 150c+10c, 48hr + 8hr* C 0hr figure 14.7 recommended screening procedure if a series of write errors occurs while the same prom writer is in use, stop programming and check the prom writer and socket adapter for defects, using a microcomputer chip with a windowed package and on-chip eprom. please inform hitachi of any abnormal conditions noted during programming or in screening of program data after high-temperature baking. rev. 3.0, 09/98, page 263 of 361 14.3.4 erasing of data the windowed package enables data to be erased by illuminating the window with ultraviolet light. table 14.7 lists the erasing conditions. table 14.7 erasing conditions item value ultraviolet wavelength 253.7 nm minimum illumination 15w s/cm 2 the conditions in table 14.7 can be satisfied by placing a 12000w/cm 2 ultraviolet lamp 2 or 3 centimeters directly above the chip and leaving it on for about 20 minutes. 14.4 handling of windowed packages (1) glass erasing window: rubbing the glass erasing window of a windowed package with a plastic material or touching it with an electrically charged object can create a static charge on the window surface which may cause the chip to malfunction. if the erasing window becomes charged, the charge can be neutralized by a short exposure to ultraviolet light. this returns the chip to its normal condition, but it also reduces the charge stored in the floating gates of the prom, so it is recommended that the chip be reprogrammed afterward. accumulation of static charge on the window surface can be prevented by the following precautions: ? when handling the package, ground yourself. dont wear gloves. avoid other possible sources of static charge. - avoid friction between the glass window and plastic or other materials that tend to accumulate static charge. ? be careful when using cooling sprays, since they may have a slight ion content. cover the window with an ultraviolet-shield label, preferably a label including a conductive material. besides protecting the prom contents from ultraviolet light, the label protects the chip by distributing static charge uniformly. (2) handling after programming: fluorescent light and sunlight contain small amounts of ultraviolet, so prolonged exposure to these types of light can cause programmed data to invert. in addition, exposure to any type of intense light can induce photoelectric effects that may lead to chip malfunction. it is recommended that after programming the chip, you cover the erasing window with a light-proof label (such as an ultraviolet-shield label). rev. 3.0, 09/98, page 264 of 361 (3) note on 84-pin lcc package: a socket should always be used when the 84-pin lcc package is mounted on a printed-circuit board. table 14.8 lists the recommended socket. table 14.8 recommended socket for mounting 84-pin lcc package manufacturer code sumitomo 3-m 284-1273-00-1102j rev. 3.0, 09/98, page 265 of 361 section 15 power-down state 15.1 overview the h8/338 series has a power-down state that greatly reduces power consumption by stopping some or all of the chip functions. the power-down state includes three modes: (1) sleep mode - a software-triggered mode in which the cpu halts but the rest of the chip remains active (2) software standby mode - a software-triggered mode in which the entire chip is inactive (3) hardware standby mode - a hardware-triggered mode in which the entire chip is inactive table 15.1 lists the conditions for entering and leaving the power-down modes. it also indicates the status of the cpu, on-chip supporting modules, etc. in each power-down mode. table 15.1 power-down state mode entering procedure clock cpu cpu regs. sup. mod. ram i/o ports exiting methods sleep mode execute sleep instruction run halt held run held held interrupt res stby software standby mode set ssby bit in syscr to 1, then execute sleep instruction halt halt held halt and initialized held held nmi irq 0 - irq 2 res stby hardware standby mode set stby pin to low level halt halt not held halt and initialized held high impedance state stby high, then res low ? high notes: 1. syscr: system control register 2. ssby: software standby bit rev. 3.0, 09/98, page 266 of 361 15.2 system control register: power-down control bits bits 7 to 4 of the system control register (syscr) concern the power-down state. specifically, they concern the software standby mode. table 15.2 lists the attributes of the system control register. table 15.2 system control register name abbreviation r/w initial value address system control register syscr r/w h'09 h'ffc4 bit:76543210 ssby sts2 sts1 sts0 ? nmieg dpme rame initial value: 0 0 0 0 1 0 0 1 read/write: r/w r/w r/w r/w ? r/w r/w r/w bit 7 ? software standby (ssby): this bit enables or disables the transition to the software standby mode. on recovery from the software standby mode by an external interrupt, ssby remains set to 1. to clear this bit, software must write a 0. bit 7 ssby description 0 the sleep instruction causes a transition to the sleep mode. (initial value) 1 the sleep instruction causes a transition to the software standby mode. bits 6 to 4 ? standby timer select 2 to 0 (sts2 to sts0): these bits select the clock settling time when the chip recovers from the software standby mode by an external interrupt. during the selected time, the clock oscillator runs but clock pulses are not supplied to the cpu or the on-chip supporting modules. bit 6 sts2 bit 5 sts1 bit 4 sts0 description 0 0 0 settling time = 8192 states (initial value) 0 0 1 settling time = 16384 states 0 1 0 settling time = 32768 states 0 1 1 settling time = 65536 states 1 ?? settling time = 131072 states rev. 3.0, 09/98, page 267 of 361 when the on-chip clock pulse generator is used, the sts bits should be set to allow a settling time of at least 10ms. table 15.3 lists the settling times selected by these bits at several clock frequencies and indicates the recommended settings. when the chip is externally clocked, the sts bits can be set to any value. the minimum value (sts2 = sts1 = sts0 = 0) is recommended. table 15.3 times set by standby timer select bits (unit: ms) system clock frequency (mhz) sts2 sts1 sts0 settling time (states) 10864210.5 0 0 0 8192 0.8 1.0 1.3 2.0 4.1 8.2 16.4 0 0 1 16384 1.6 2.0 2.7 4.1 8.2 16.4 32.8 0 1 0 32768 3.3 4.1 5.5 8.2 16.4 32.8 65.5 0 1 1 65536 6.6 8.2 10.9 16.4 32.8 65.5 131.1 1 ?? 131072 13.1 16.4 21.8 32.8 65.5 131.1 262.1 notes: 1. all times are in milliseconds. 2. recommended values are printed in boldface. rev. 3.0, 09/98, page 268 of 361 15.3 sleep mode the sleep mode provides an effective way to conserve power while the cpu is waiting for an external interrupt or an interrupt from an on-chip supporting module. 15.3.1 transition to sleep mode when the ssby bit in the system control register is cleared to 0, execution of the sleep instruction causes a transition from the program execution state to the sleep mode. after executing the sleep instruction, the cpu halts, but the contents of its internal registers remain unchanged. the on-chip supporting modules continue to operate normally. 15.3.2 exit from sleep mode the chip wakes up from the sleep mode when it receives an internal or external interrupt request, or a low input at the res or stby pin. (1) wake-up by interrupt: an interrupt releases the sleep mode and starts the cpus interrupt- handling sequence. if an interrupt from an on-chip supporting module is disabled by the corresponding enable/disable bit in the modules control register, the interrupt cannot be requested, so it cannot wake the chip up. similarly, the cpu cannot be awoken by an interrupt other than nmi if the i (interrupt mask) bit in the ccr (condition code register) is set when the sleep instruction is executed. (2) wake-up by res pin: when the res pin goes low, the chip exits from the sleep mode to the reset state. (3) wake-up by stby pin: when the stby pin goes low, the chip exits from the sleep mode to the hardware standby mode. rev. 3.0, 09/98, page 269 of 361 15.4 software standby mode in the software standby mode, the system clock stops and chip functions halt, including both cpu functions and the functions of the on-chip supporting modules. power consumption is reduced to an extremely low level. the on-chip supporting modules and their registers are reset to their initial states, but as long as a minimum necessary voltage supply is maintained (at least 2v), the contents of the cpu registers and on-chip ram remain unchanged. 15.4.1 transition to software standby mode to enter the software standby mode, set the standby bit (ssby) in the system control register (syscr) to 1, then execute the sleep instruction. 15.4.2 exit from software standby mode the chip can be brought out of the software standby mode by an input at one of six pins: nmi , irq 0 , irq 1 , irq 2 , res , or stby . (1) recovery by external interrupt: when an nmi , irq 0 , irq 1 , or irq 2 request signal is received, the clock oscillator begins operating. after the waiting time set in the system control register (bits sts2 to sts0), clock pulses are supplied to the cpu and on-chip supporting modules. the cpu executes the interrupt-handling sequence for the requested interrupt, then returns to the instruction after the sleep instruction. the ssby bit is not cleared. see section 15.2, system control register: power-down control bits, for information about the sts bits. interrupts irq 3 to irq 7 should be disabled before entry to the software standby mode. clear irq 3 e to irq 7 e to 0 in the interrupt enable register (ier). (2) recovery by res pin: when the res pin goes low, the clock oscillator starts and clock pulses are supplied to the entire chip. next, when the res pin goes high, the cpu begins executing the reset sequence. the ssby bit is cleared to 0. the res pin must be held low long enough for the clock to stabilize. (3) recovery by stby pin: when the stby pin goes low, the chip exits from the software standby mode to the hardware standby mode. rev. 3.0, 09/98, page 270 of 361 15.4.3 sample application of software standby mode in this example the chip enters the software standby mode when nmi goes low and exits when nmi goes high, as shown in figure 15.1. the nmi edge bit (nmieg) in the system control register is originally cleared to 0, selecting the falling edge. when nmi goes low, the nmi interrupt handling routine sets nmieg to 1, sets ssby to 1 (selecting the rising edge), then executes the sleep instruction. the chip enters the software standby mode. it recovers from the software standby mode on the next rising edge of nmi . clock generator ? nmi nmieg ssby nmi interrupt handler nmieg = "1" ssby = "1" software standby mode (power-down state) sleep nmi interrupt handler settling time figure 15.1 nmi timing in software standby mode rev. 3.0, 09/98, page 271 of 361 15.4.4 application note 1. the i/o ports retain their current states in the software standby mode. if a port is in the high output state, the current dissipation caused by the high output current is not reduced. 2. when software standby mode is entered under condition (a) or (b) below, current dissipation is higher (i cc = 100 to 300 a) than normal in standby mode. (a) in single-chip mode (mode 3): when software standby mode is entered by executing an instruction stored in on-chip rom, after even one instruction not stored in on-chip rom has been fetched (e.g. from on-chip ram). (b) in expanded mode with on-chip rom enabled (mode 2): when software standby mode is entered by executing an instruction stored in on-chip rom, after even one instruction not stored in on-chip rom has been fetched (e.g. from external memory or on-chip ram). note that the h8/300 cpu pre-fetches instructions. if an instruction stored in the last two bytes of on-chip rom is executed, the contents of the next two bytes, not in on-chip rom, will be fetched as the next instruction. this problem does not occur in expanded mode when on-chip rom is disabled (mode 1). in hardware standby mode there is no additional current dissipation, regardless of the conditions when hardware standby mode is entered. rev. 3.0, 09/98, page 272 of 361 15.5 hardware standby mode 15.5.1 transition to hardware standby mode regardless of its current state, the chip enters the hardware standby mode whenever the stby pin goes low. the hardware standby mode reduces power consumption drastically by halting the cpu, stopping all the functions of the on-chip supporting modules, and placing i/o ports in the high-impedance state. the registers of the on-chip supporting modules are reset to their initial values. only the on-chip ram is held unchanged, provided the minimum necessary voltage supply is maintained (at least 2v). notes: 1. the rame bit in the system control register should be cleared to 0 before the stby pin goes low, to disable the on-chip ram during the hardware standby mode. 2. do not change the inputs at the mode pins (md1, md0) during hardware standby mode. be particularly careful not to let both mode pins go low in hardware standby mode, since that places the chip in prom mode and increases current dissipation. 15.5.2 recovery from hardware standby mode recovery from the hardware standby mode requires inputs at both the stby and res pins. when the stby pin goes high, the clock oscillator begins running. the res pin should be low at this time and should be held low long enough for the clock to stabilize. when the res pin changes from low to high, the reset sequence is executed and the chip returns to the program execution state. 15.5.3 timing relationships figure 15.2 shows the timing relationships in the hardware standby mode. in the sequence shown, first res goes low, then stby goes low, at which point the chip enters the hardware standby mode. to recover, first stby goes high, then after the clock settling time, res goes high. rev. 3.0, 09/98, page 273 of 361 clock pulse generator res stby restart clock settling time figure 15.2 hardware standby mode timing rev. 3.0, 09/98, page 274 of 361 rev. 3.0, 09/98, page 275 of 361 section 16 electrical specifications 16.1 absolute maximum ratings table 16.1 lists the absolute maximum ratings. table 16.1 absolute maximum ratings item symbol rating unit supply voltage v cc - 0.3 to +7.0 v programming voltage v pp - 0.3 to +13.5 v input voltage ports 1 - 6, 8, 9 v in - 0.3 to v cc + 0.3 v port 7 v in - 0.3 to av cc + 0.3 v analog supply voltage av cc - 0.3 to +7.0 v analog input voltage v an - 0.3 to av cc + 0.3 v operating temperature t opr regular specifications: - 20 to +75 c wide-range specifications: - 40 to +85 c storage temperature t stg - 55 to +125 c note: exceeding the absolute maximum ratings shown in table 16.1 can permanently destroy the chip. 16.2 electrical characteristics 16.2.1 dc characteristics table 16.2 lists the dc characteristics of the 5v version. table 16.3 lists the dc characteristics of the 3v version. table 16.4 gives the allowable current output values of the 5v version. table 16.5 gives the allowable current output values of the 3v version. rev. 3.0, 09/98, page 276 of 361 table 16.2 dc characteristics (5v version) conditions: v cc = 5.0v 10%, av cc = 5.0v 10%*, v ss = av ss = 0v, ta = - 20 to 75 c (regular specifications), ta = - 40 to 85 c (wide-range specifications) item symbol min typ max unit measurement conditions 1.0 ?? v ?? v cc 0.7 v schmitt trigger input voltage (1) p6 7 - p6 2 , p6 0 , p8 6 - p8 0 , p9 7 , p9 4 - p9 0 v t - v t + v t + - v t - 0.4 ?? v res , stby , nmi md 1 , md 0 extal v cc - 0.7 ? v cc + 0.3 v input high voltage (2) p7 7 - p7 0 v ih 2.0 ? av cc + 0.3 v input high voltage input pins other than (1) and (2) v ih 2.0 ? v cc + 0.3 v input low voltage (3) res , stby md 1 , md 0 v il - 0.3 ? 0.5 v input low voltage input pins other than (1) and (3) above v il - 0.3 ? 0.8 v v cc - 0.5 ?? vi oh = - 200a output high voltage all output pins v oh 3.5 ?? vi oh = - 1.0ma all output pins ?? 0.4 v i ol = 1.6ma output low voltage ports 1 and 2 v ol ?? 1.0 v i ol = 10.0ma res ?? 10.0 a stby , nmi , md 1 , md 0 ?? 1.0 a v in = 0.5v to v cc - 0.5v input leakage current p7 7 - p7 0 |i in | ?? 1.0 a v in = 0.5v to av cc - 0.5v leakage current in 3-state (off state) ports 1, 2, 3, 4, 5, 6, 8, 9 |i tsi | ?? 1.0 a v in = 0.5v to v cc - 0.5v input pull-up mos current ports 1, 2, 3 - ip 30 ? 250 a v in = 0v note: connect av cc to the power supply (v cc ) even when the a/d and d/a converters are not used. rev. 3.0, 09/98, page 277 of 361 table 16.2 dc characteristics (5v version) (cont) conditions: v cc = av cc = 5.0v 10%, v ss = av ss = 0v, ta = - 20 to 75 c (regular specifications), ta = - 40 to 85 c (wide-range specifications) item symbol min typ max unit measurement conditions res (v pp ) ?? 60 pf nmi ?? 30 pf input capacitance all input pins except res and nmi c in ?? 15 pf v in = 0v f = 1mhz ta = 25 c ? 12 25 ma f = 6mhz ? 16 30 ma f = 8mhz current dissipation * 1 normal operation i cc ? 20 40 ma f = 10mhz ? 815maf = 6mhz ? 10 20 ma f = 8mhz sleep mode ? 12 25 ma f = 10mhz standby modes * 2 ? 0.01 5.0 a analog supply current during a/d or d/a conversion ai cc ? 2.0 5.0 ma waiting ? 0.01 5.0 a ram standby voltage v ram 2.0 ?? v notes: 1. current dissipation values assume that v ih min = v cc - 0.5v, v il max = 0.5v, all output pins are in the no-load state, and all input pull-up transistors are off. 2. for these values it is assumed that v ram v cc < 4.5v and v ih min = v cc 0.9, v il max = 0.3v. rev. 3.0, 09/98, page 278 of 361 table 16.3 dc characteristics (3v version) conditions: v cc = 3.0v 10%, av cc = 5.0v 10%* 1 , v ss = av ss = 0v, ta = - 20 to 70 c item symbol min typ max unit measurement conditions v t - v cc 0.15 ?? v v t + ?? v cc 0.7 v schmitt trigger input voltage * 2 (1) p6 7 - p6 2 , p6 0 , p8 6 - p8 0 , p9 7 , p9 4 - p9 0 v t + - v t - 0.2 ?? v res , stby v cc 0.9 ? v cc + 0.3 v md 1 , md 0 extal, nmi p7 7 - p7 0 v cc 0.7 ? av cc + 0.3 v input high voltage * 2 (2) input pins other than (1) and (2) above v ih v cc 0.7 ? v cc + 0.3 v res , stby md 1 , md 0 - 0.3 ? v cc 0.1 v input low voltage * 2 (3) input pins other than (1) and (3) above v il - 0.3 ? v cc 0.15 v v cc - 0.4 ?? vi oh = - 200a output high voltage all output pins v oh v cc - 0.9 ?? vi oh = - 1.0ma all output pins ?? 0.4 v i ol = 0.8ma output low voltage ports 1 and 2 v ol ?? 0.4 v i ol = 1.6ma res ?? 10.0 a stby , nmi , md 1 , md 0 ?? 1.0 a v in = 0.5 to v cc - 0.5v input leakage current p7 7 - p7 0 |i in | ?? 1.0 a v in = 0.5 to av cc - 0.5v leakage current in 3-state (off state) ports 1, 2, 3, 4, 5, 6, 8, 9 |i tsi | ?? 1.0 a v in = 0.5 to v cc - 0.5v input pull-up mos current ports 1, 2, 3 - ip 3 ? 120 a v in = 5.0v notes: 1. connect av cc to the power supply (v cc ) even when the a/d and d/a converters are not used. 2. in the range 3.3v < v cc < 4.5v, for the input levels of v ih and v t + , apply the higher of the values given for the 5v and 3v versions. for v il and v t - , apply the lower of the values given for the 5v and 3v versions. rev. 3.0, 09/98, page 279 of 361 table 16.3 dc characteristics (3v version) (cont) conditions: v cc = 3.0v 10%, av cc = 5.0v 10%* 1 , v ss = av ss = 0v, ta = - 20 to 70 c item symbol min typ max unit measurement conditions res ?? 60 pf v in = 0v nmi ?? 30 pf f = 1mhz input capacitance all input pins except res and nmi c in ?? 15 pf ta = 25 c normal operation ? 6 ? ma f = 3mhz ? 10 20 ma f = 5mhz sleep mode ? 4 ? ma f = 3mhz ? 612maf = 5mhz current dissipation * 1 standby modes * 2 i cc ? 0.01 5.0 a analog supply current during a/d or d/a conversion ai cc ? 2.0 5.0 ma waiting ? 0.01 5.0 a ram backup voltage (in standby modes) v ram 2.0 ?? v notes: 1. current dissipation values assume that v ih min = v cc - 0.5v, v il max = 0.5v, all output pins are in the no-load state, and all input pull-up transistors are off. 2. for these values it is assumed that v ram v cc < 2.7v and v ih min = v cc 0.9, v il max = 0.3v. rev. 3.0, 09/98, page 280 of 361 table 16.4 allowable output current values (5v version) conditions: v cc = av cc = 5.0v 10%, v ss = av ss = 0v, ta = - 20 to 75 c (regular specifications), ta = - 40 to 85 c (wide-range specifications) item symbol min typ max unit ports 1 and 2 ?? 10 ma allowable output low current (per pin) other output pins i ol ?? 2.0 ma ports 1 and 2, total ?? 80 ma allowable output low current (total) total of all output s iol ?? 120 ma allowable output high current (per pin) all output pins - i oh ?? 2.0 ma allowable output high current (total) total of all output s- i oh ?? 40 ma table 16.5 allowable output current values (3v version) conditions: v cc = 3.0v 10%, av cc = 5.0v 10%, v ss = av ss = 0v, ta = - 20 to 75 c item symbol min typ max unit ports 1 and 2 ?? 2ma allowable output low current (per pin) other output pins i ol ?? 1ma ports 1 and 2, total ?? 40 ma allowable output low current (total) total of all output s i ol ?? 60 ma allowable output high current (per pin) all output pins - i oh ?? 2ma allowable output high current (total) total of all output s- i oh ?? 30 ma note: to avoid degrading the reliability of the chip, be careful not to exceed the output current values in tables 16.4 and 16.5. in particular, when driving a darlington transistor pair or led directly, be sure to insert a current-limiting resistor in the output path. see figures 16.1 and 16.2. rev. 3.0, 09/98, page 281 of 361 h8/338 darlington pair port 2 k figure 16.1 example of circuit for driving a darlington pair (5v version) h8/338 port 1 or 2 v cc led 600 figure 16.2 example of circuit for driving an led (5v version) 16.2.2 ac characteristics the ac characteristics are listed in three tables. bus timing parameters are given in table 16.6, control signal timing parameters in table 16.7, and timing parameters of the on-chip supporting modules in table 16.8. rev. 3.0, 09/98, page 282 of 361 table 16.6 bus timing condition a: v cc = 5.0v 10%, v ss = 0v, f = 0.5mhz to maximum operating frequency, ta = - 20 to 75 c (regular specifications), ta = - 40 to 85 c (wide-range specifications) condition b: v cc = 3.0v 10%, v ss = 0v, f = 0.5mhz to maximum operating frequency, ta = - 20 to 75 c condition b condition a 5mhz 6mhz 8mhz 10mhz item symbol min max min max min max min max unit measurement conditions clock cycle time t cyc 200 2000 166.7 2000 125 2000 100 2000 ns fig. 16.4 clock pulse width low t cl 70 ? 65 ? 45 ? 35 ? ns fig. 16.4 clock pulse width high t ch 70 ? 65 ? 45 ? 35 ? ns fig. 16.4 clock rise time t cr ? 25 ? 15 ? 15 ? 15 ns fig. 16.4 clock fall time t cf ? 25 ? 15 ? 15 ? 15 ns fig. 16.4 address delay time t ad ? 90 ? 70 ? 60 ? 50 ns fig. 16.4 address hold time t ah 30 ? 30 ? 25 ? 20 ? ns fig. 16.4 address strobe delay time t asd ? 80 ? 70 ? 60 ? 40 ns fig. 16.4 write strobe delay time t wsd ? 80 ? 70 ? 60 ? 50 ns fig. 16.4 strobe delay time t sd ? 90 ? 70 ? 60 ? 50 ns fig. 16.4 write strobe pulse width * t wsw 200 ? 200 ? 150 ? 120 ? ns fig. 16.4 address setup time 1 * t as1 25 ? 25 ? 20 ? 15 ? ns fig. 16.4 address setup time 2 * t as2 105 ? 105 ? 80 ? 65 ? ns fig. 16.4 read data setup time t rds 90 ? 70 ? 50 ? 35 ? ns fig. 16.4 read data hold time * t rdh 0 ? 0 ? 0 ? 0 ? ns fig. 16.4 read data access time * t acc ? 300 ? 270 ? 210 ? 170 ns fig. 16.4 write data delay time t wdd ? 125 ? 85 ? 75 ? 75 ns fig. 16.4 write data setup time t wds 10 ? 20 ? 10 ? 5 ? ns fig. 16.4 write data hold time t wdh 30 ? 30 ? 25 ? 20 ? ns fig. 16.4 wait setup time t wts 60 ? 40 ? 40 ? 40 ? ns fig. 16.5 wait hold time t wth 20 ? 10 ? 10 ? 10 ? ns fig. 16.5 note: values at maximum operating frequency rev. 3.0, 09/98, page 283 of 361 table 16.7 control signal timing condition a: v cc = 5.0v 10%, v ss = 0v, f = 0.5mhz to maximum operating frequency, ta = - 20 to 75 c (regular specifications), ta = - 40 to 85 c (wide-range specifications) condition b: v cc = 3.0v 10%, v ss = 0v, f = 0.5mhz to maximum operating frequency, ta = - 20 to 75 c condition b condition a 5mhz 6mhz 8mhz 10mhz item symbol min max min max min max min max unit measurement conditions res setup time t ress 300 ? 200 ? 200 ? 200 ? ns fig. 16.6 res pulse width t resw 10 ? 10 ? 10 ? 10 ? tcyc fig. 16.6 nmi setup time ( nmi , irq 0 to irq 7 ) t nmis 300 ? 150 ? 150 ? 150 ? ns fig. 16.7 nmi hold time ( nmi , irq 0 to irq 7 ) t nmih 10 ? 10 ? 10 ? 10 ? ns fig. 16.7 interrupt pulse width for recovery from software standby mode ( nmi , irq 0 to irq 2 ) t nmiw 300 ? 200 ? 200 ? 200 ? ns fig. 16.7 crystal oscillator settling time (reset) t osc1 20 ? 20 ? 20 ? 20 ? ms fig. 16.8 crystal oscillator settling time (software standby) t osc2 10 ? 10 ? 10 ? 10 ? ms fig. 16.9 rev. 3.0, 09/98, page 284 of 361 table 16.8 timing conditions of on-chip supporting modules condition a: v cc = 5.0v 10%, v ss = 0v, f = 0.5mhz to maximum operating frequency, ta = - 20 to 75 c (regular specifications), ta = - 40 to 85 c (wide-range specifications) condition b: v cc = 3.0v 10%, v ss = 0v, f = 0.5mhz to maximum operating frequency, ta = - 20 to 75 c condition b condition a 5mhz 6mhz 8mhz 10mhz item symbol min max min max min max min max unit measurement conditions frt timer output delay time t ftod ? 150 ? 100 ? 100 ? 100 ns fig. 16.10 timer input setup time t ftis 80 ? 50 ? 50 ? 50 ? ns fig. 16.10 timer clock input setup time t ftcs 80 ? 50 ? 50 ? 50 ? ns fig. 16.11 timer clock pulse width t ftcwh t ftcwl 1.5 ? 1.5 ? 1.5 ? 1.5 ? tcyc fig. 16.11 tmr timer output delay time t tmod ? 150 ? 100 ? 100 ? 100 ns fig. 16.12 timer reset input setup time t tmrs 80 ? 50 ? 50 ? 50 ? ns fig. 16.14 timer clock input setup time t tmcs 80 ? 50 ? 50 ? 50 ? ns fig. 16.13 timer clock pulse width (single edge) t tmcwh 1.5 ? 1.5 ? 1.5 ? 1.5 ? tcyc fig. 16.13 timer clock pulse width (both edges) t tmcwl 2.5 ? 2.5 ? 2.5 ? 2.5 ? tcyc fig. 16.13 pwm timer output delay time t pwod ? 150 ? 100 ? 100 ? 100 ns fig. 16.15 (async) t scyc 4 ? 4 ? 4 ? 4 ? tcyc fig. 16.16 sci input clock cycle (sync) t scyc 6 ? 6 ? 6 ? 6 ? tcyc fig. 16.16 transmit data delay time (sync) t txd ? 200 ? 100 ? 100 ? 100 ns fig. 16.16 receive data setup time (sync) t rxs 150 ? 100 ? 100 ? 100 ? ns fig. 16.16 receive data hold time (sync) t rxh 150 ? 100 ? 100 ? 100 ? ns fig. 16.16 input clock pulse width t sckw 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tscyc fig. 16.17 rev. 3.0, 09/98, page 285 of 361 table 16.8 timing conditions of on-chip supporting modules (cont) condition a: v cc = 5.0v 10%, v ss = 0v, f = 0.5mhz to maximum operating frequency, ta = - 20 to 75 c (regular specifications), ta = - 40 to 85 c (wide-range specifications) condition b: v cc = 3.0v 10%, v ss = 0v, f = 0.5mhz to maximum operating frequency, ta = - 20 to 75 c condition b condition a 5mhz 6mhz 8mhz 10mhz item symbol min max min max min max min max unit measurement conditions ports output data delay time t pwd ? 150 ? 100 ? 100 ? 100 ns fig. 16.18 input data setup time t prs 80 ? 50 ? 50 ? 50 ? ns fig. 16.18 input data hold time t prh 80 ? 50 ? 50 ? 50 ? ns fig. 16.18 measurement conditions for ac characteristics lsi output pin r h 5v r l c input/output timing reference levels low: high: 0.8v 2.0v c= r l = r h = 90pf: ports1-4, 6, 9 30pf: ports5, 8 2.4 k 12 k figure 16.3 output load circuit rev. 3.0, 09/98, page 286 of 361 16.2.3 a/d converter characteristics table 16.9 lists the characteristics of the on-chip a/d converter. table 16.9 a/d converter characteristics condition a: v cc = 5.0v 10%, av cc = 5.0v 10%, v ss = av ss = 0v, f = 0.5mhz to maximum operating frequency, ta = - 20 to 75 c (regular specifications), ta = - 40 to 85 c (wide-range specifications) condition b: v cc = 3.0v 10%, av cc = 5.0v 10%, v ss = av ss = 0v, f = 0.5mhz to maximum operating frequency, ta = - 20 to 75 c condition b condition a 5mhz 6mhz 8mhz 10mhz item min typ max min typ max min typ max min typ max unit resolution 888888888888bits conversion time (single mode) * ?? 24.4 ?? 20.4 ?? 15.25 ?? 12.2 s analog input capacitance ?? 20 ?? 20 ?? 20 ?? 20 pf allowable signal source impedance ?? 10 ?? 10 ?? 10 ?? 10 k w nonlinearity error ?? 1 ?? 1 ?? 1 ?? 1 lsb offset error ?? 1 ?? 1 ?? 1 ?? 1 lsb full-scale error ?? 1 ?? 1 ?? 1 ?? 1 lsb quantizing error ?? 0.5 ?? 0.5 ?? 0.5 ?? 0.5 lsb absolute accuracy ?? 1.5 ?? 1.5 ?? 1.5 ?? 1.5 lsb note: values at maximum operating frequency rev. 3.0, 09/98, page 287 of 361 16.2.4 d/a converter characteristics table 16.10 lists the characteristics of the on-chip d/a converter. table 16.10 d/a converter characteristics condition a: v cc = 5.0v 10%, av cc = 5.0v 10%, v ss = av ss = 0v, f = 0.5mhz to maximum operating frequency, ta = - 20 to 75 c (regular specifications), ta = - 40 to 85 c (wide-range specifications) condition b: v cc = 3.0v 10%, av cc = 5.0v 10%, v ss = av ss = 0v, f = 0.5mhz to maximum operating frequency, ta = - 20 to 75 c condition b condition a 5mhz 6mhz 8mhz 10mhz item min typ max min typ max min typ max min typ max unit measurement conditions resolution 888888888888bits conversion time ?? 10.0 ?? 10.0 ?? 10.0 ?? 10.0 s 30pf load capacitance ? 1 1.5 ? 1 1.5 ? 1 1.5 ? 1 1.5 lsb 2m w load resistance absolute accuracy ?? 1 ?? 1 ?? 1 ?? 1 lsb 4m w load resistance 16.3 mcu operational timing this section provides the following timing charts: 16.3.1 bus timing figures 16.4 to 16.5 16.3.2 control signal timing figures 16.6 to 16.9 16.3.3 16-bit free-running timer timing figures 16.10 to 16.11 16.3.4 8-bit timer timing figures 16.12 to 16.14 16.3.5 pwm timer timing figure 16.15 16.3.6 sci timing figures 16.16 to 16.17 16.3.7 i/o port timing figure 16.18 rev. 3.0, 09/98, page 288 of 361 16.3.1 bus timing (1) basic bus cycle (without wait states) in expanded modes ? a 15 + a 0 as, rd d 7 to d 0 (read) d 7 to d 0 (write) wr t ch t ad t cr t cyc t 1 t cl t cf t asd t asi t sc t rdh t rds t sd t wsw t wsd t as2 t ah t wds t wdd t wdh t acc t ah t 2 t 3 figure 16.4 basic bus cycle (without wait states) in expanded modes rev. 3.0, 09/98, page 289 of 361 (2) basic bus cycle (with 1 wait state) in expanded modes ? a 15 + a 0 as, rd d 7 to d 0 (read) d 7 to d 0 (write) wr t 1 wait t 2 t w t 3 t wts t wth t wts t wth figure 16.5 basic bus cycle (with 1 wait state) in expanded modes rev. 3.0, 09/98, page 290 of 361 16.3.2 control signal timing (1) reset input timing ? res t ress t ress t resw figure 16.6 reset input timing (2) interrupt input timing ? irq l (level) nmi irq i nmi irq e (edge) note: i = 0 to 7; irq e : irq i when edge-sensed; irq l : irq i when level-sensed? t nmis t nmis t nmih t nmiw figure 16.7 interrupt input timing rev. 3.0, 09/98, page 291 of 361 (3) clock settling timing ? res stby vcc t osc1 t osc1 figure 16.8 clock settling timing (4) clock settling timing for recovery from software standby mode nmi irq ( i = 0, 1, 2) t osc2 ? figure 16.9 clock settling timing for recovery from software standby mode rev. 3.0, 09/98, page 292 of 361 16.3.3 16-bit free-running timer timing (1) free-running timer input/output timing ? free-running timer counter compare-match ftoa, ftob ftia , ftib, ftic, ftid t ftod t ftis figure 16.10 free-running timer input/output timing (2) external clock input timing for free-running timer ? ftci t ftcs t ftcwh t ftcwl figure 16.11 external clock input timing for free-running timer rev. 3.0, 09/98, page 293 of 361 16.3.4 8-bit timer timing (1) 8-bit timer output timing ? timer counter compare-match tmc 0, tmc 1 t tmod figure 16.12 8-bit timer output timing (2) 8-bit timer clock input timing ? tmci 0 tmci 1 t tmcs t tmcs t tmcwh t tmcwl figure 16.13 8-bit timer clock input timing (3) 8-bit timer reset input timing ? tmri 0 , tmri 1 timer counter n t tmrs n' 00 figure 16.14 8-bit timer reset input timing rev. 3.0, 09/98, page 294 of 361 16.3.5 pulse width modulation timer timing ? timer counter compare-match pw 0, pw 1 t pwod figure 16.15 pwm timer output timing 16.3.6 serial communication interface timing (1) sci input/output timing serial clock (sck 0 , sck 1 ) transmit data (t x d 0 , t x d 1 ) receive data (r x d 0 , r x d 1 ) t scyc t txd t rxh t rxs figure 16.16 sci input/output timing (synchronous mode) (2) sci input clock timing sck 0 , sck 1 t sckw t scyc figure 16.17 sci input clock timing rev. 3.0, 09/98, page 295 of 361 16.3.7 i/o port timing t prh ? port 1 to port 9 (input) port 1* to port 9 (output) t 1 t 2 t prs t pwd t 3 note: * except p9 6 and p7 7 to p7 0 figure 16.18 i/o port input/output timing rev. 3.0, 09/98, page 296 of 361 rev. 3.0, 09/98, page 297 of 361 appendix a cpu instruction set a.1 instruction set list operation notation rd8/16 general register (destination) (8 or 16 bits) rs8/16 general register (source) (8 or 16 bits) rn8/16 general register (8 or 16 bits) ccr condition code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #xx:3/8/16 immediate data (3, 8, or 16 bits) d:8/16 displacement (8 or 16 bits) @aa:8/16 absolute address (8 or 16 bits) + addition - subtraction multiplication ? division and logical or logical ? exclusive or logical ? move ? not condition code notation b modified according to the instruction result * undetermined (unpredictable) 0 always cleared to 0 ? not affected by the instruction result rev. 3.0, 09/98, page 298 of 361 table a.1 instruction set mnemonic operation addressing mode/ instruction length operand size #xx: 8/16 rn @rn @(d:16, rn) @Crn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states ihnzvc condition code ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mov.b #xx:8, rd mov.b rs, rd mov.b @rs, rd mov.b @(d:16, rs), rd mov.b @rs+, rd mov.b @aa:8, rd mov.b @aa:16, rd mov.b rs, @rd mov.b rs, @(d:16, rd) mov.b rs, @Crd mov.b rs, @aa:8 mov.b rs, @aa:16 mov.w #xx:16, rd mov.w rs, rd mov.w @rs, rd mov.w @(d:16, rs), rd mov.w @rs+, rd mov.w @aa:16, rd mov.w rs, @rd mov.w rs, @(d:16, rd) mov.w rs, @Crd mov.w rs, @aa:16 pop rd push rs #xx:8 ? rd8 rs8 ? rd8 @rs16 ? rd8 @(d:16, rs16) ? rd8 @rs16 ? rd8 rs16+1 ? rs16 @aa:8 ? rd8 @aa:16 ? rd8 rs8 ? @rd16 rs8 ? @(d:16, rd16) rd16C1 ? rd16 rs8 ? @rd16 rs8 ? @aa:8 rs8 ? @aa:16 #xx:16 ? rd rs16 ? rd16 @rs16 ? rd16 @(d:16, rs16) ? rd16 @rs16 ? rd16 rs16+2 ? rs16 @aa:16 ? rd16 rs16 ? @rd16 rs16 ? @(d:16, rd16) rd16C2 ? rd16 rs16 ? @rd16 rs16 ? @aa:16 @sp ? rd16 sp+2 ? sp spC2 ? sp rs16 ? @sp b b b b b b b b b b b b w w w w w w w w w w w w 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 4 6 6 4 6 4 6 6 4 6 4 2 4 6 6 6 4 6 6 6 6 6 2 2 4 2 2 4 2 4 2 2 4 4 2 2 4 2 4 2 4 2 4 2 ? ? 20 rev. 3.0, 09/98, page 299 of 361 table a.1 instruction set (cont) mnemonic operation addressing mode/ instruction length operand size #xx: 8/16 rn @rn @(d:16, rn) @Crn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states ihnzvc condition code eepmov add.b #xx:8, rd add.b rs, rd add.w rs, rd addx.b #xx:8, rd addx.b rs, rd adds.w #1, rd adds.w #2, rd inc.b rd daa.b rd sub.b rs, rd sub.w rs, rd subx.b #xx:8, rd subx.b rs, rd subs.w #1, rd subs.w #2, rd dec.b rd das.b rd neg.b rd cmp.b #xx:8, rd cmp.b rs, rd cmp.w rs, rd mulxu.b rs, rd movfpe@aa:16, rd movtpe rs, @aa:16 if r4l 1 0 then repeat @r5 ? @r6 r5+1 ? r5 r6+1 ? r6 r4lC1 ? r4l until r4l=0 else next; rd8+#xx:8 ? rd8 rd8+rs8 ? rd8 rd16+rs16 ? rd16 rd8+#xx:8 +c ? rd8 rd8+rs8 +c ? rd8 rd16+1 ? rd16 rd16+2 ? rd16 rd8+1 ? rd8 rd8 decimal adjust ? rd8 rd8Crs8 ? rd8 rd16Crs16 ? rd16 rd8C#xx:8 Cc ? rd8 rd8Crs8 Cc ? rd8 rd16C1 ? rd16 rd16C2 ? rd16 rd8C1 ? rd8 rd8 decimal adjust ? rd8 0Crd ? rd rd8C#xx:8 rd8Crs8 rd16Crs16 rd8 rs8 ? rd16 b b w b b w w b b b w b b w w b b b b b w b (4) 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 14 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? (1) ? ? ? ? (2) ? ? ? (2) ? ? ? ? ? ? ** (3) ? ? ? ? ? ? ? (1) ? ? ? ? (2) ? ? ? ? (2) ? ? ? ? ? ? ? ** ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (1) ? ? ? ? ? ? rev. 3.0, 09/98, page 300 of 361 table a.1 instruction set (cont) mnemonic operation addressing mode/ instruction length operand size #xx: 8/16 rn @rn @(d:16, rn) @Crn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states ihnzvc condition code ? ? divxu.b rs, rd and.b #xx:8, rd and.b rs, rd or.b #xx:8, rd or.b rs, rd xor.b #xx:8, rd xor.b rs, rd not.b rd shal.b rd shar.b rd shll.b rd shlr.b rd rotxl.b rd rotxr.b rd rotl.b rd rotr.b rd rd16 ? rs8 ? rd16 (rdh: remainder, rdl: quotient) rd8 #xx:8 ? rd8 rd8 rs8 ? rd8 rd8 #xx:8 ? rd8 rd8 rs8 ? rd8 rd8 ? #xx:8 ? rd8 rd8 ? rs8 ? rd8 rd ? rd b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 (6) 7) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? b 7 b 0 0 c b 7 b 0 0 c c b 7 b 0 b 7 b 0 0c c b 7 b 0 c b 7 b 0 c b 7 b 0 c b 7 b 0 rev. 3.0, 09/98, page 301 of 361 table a.1 instruction set (cont) mnemonic operation addressing mode/ instruction length operand size #xx: 8/16 rn @rn @(d:16, rn) @Crn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states ihnzvc condition code ? bset #xx:3, rd bset #xx:3, @rd bset #xx:3, @aa:8 bset rn, rd bset rn, @rd bset rn, @aa:8 bclr #xx:3, rd bclr #xx:3, @rd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @rd bclr rn, @aa:8 bnot #xx:3, rd bnot #xx:3, @rd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @rd bnot rn, @aa:8 btst #xx:3, rd btst #xx:3, @rd btst #xx:3, @aa:8 btst rn, rd btst rn, @rd btst rn, @aa:8 (#xx:3 of rd8) ? 1 (#xx:3 of @rd16) ? 1 (#xx:3 of @aa:8) ? 1 (rn8 of rd8) ? 1 (rn8 of @rd16) ? 1 (rn8 of @aa:8) ? 1 (#xx:3 of rd8) ? 0 (#xx:3 of @rd16) ? 0 (#xx:3 of @aa:8) ? 0 (rn8 of rd8) ? 0 (rn8 of @rd16) ? 0 (rn8 of @aa:8) ? 0 (#xx:3 of rd8) ? (#xx:3 of rd8) (#xx:3 of @rd16) ? (#xx:3 of @rd16) (#xx:3 of @aa:8) ? (#xx:3 of @aa:8) (rn8 of rd8) ? (rn8 of rd8) (rn8 of @rd16) ? (rn8 of @rd16) (rn8 of @aa:8) ? (rn8 of @aa:8) (#xx:3 of rd8) ? z (#xx:3 of @rd16) ? z (#xx:3 of @aa:8) ? z (rn8 of rd8) ? z (rn8 of @rd16) ? z (rn8 of @aa:8) ? z b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 8 8 2 6 6 2 6 6 ? ? ? ? ? rev. 3.0, 09/98, page 302 of 361 table a.1 instruction set (cont) mnemonic operation addressing mode/ instruction length operand size #xx: 8/16 rn @rn @(d:16, rn) @Crn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states ihnzvc condition code ? bld #xx:3, rd bld #xx:3, @rd bld #xx:3, @aa:8 bild #xx:3, rd bild #xx:3, @rd bild #xx:3, @aa:8 bst #xx:3, rd bst #xx:3, @rd bst #xx:3, @aa:8 bist #xx:3, rd bist #xx:3, @rd bist #xx:3, @aa:8 band #xx:3, rd band #xx:3, @rd band #xx:3, @aa:8 biand #xx:3, rd biand #xx:3, @rd biand #xx:3, @aa:8 bor #xx:3, rd bor #xx:3, @rd bor #xx:3, @aa:8 bior #xx:3, rd bior #xx:3, @rd bior #xx:3, @aa:8 bxor #xx:3, rd bxor #xx:3, @rd bxor #xx:3, @aa:8 bixor #xx:3, rd (#xx:3 of rd8) ? c (#xx:3 of @rd16) ? c (#xx:3 of @aa:8) ? c (#xx:3 of rd8) ? c (#xx:3 of @rd16) ? c (#xx:3 of @aa:8) ? c c ? (#xx:3 of rd8) c ? (#xx:3 of @rd16) c ? (#xx:3 of @aa:8) c ? (#xx:3 of rd8) c ? (#xx:3 of @rd16) c ? (#xx:3 of @aa:8) c (#xx:3 of rd8) ? c c (#xx:3 of @rd16) ? c c (#xx:3 of @aa:8) ? c c (#xx:3 of rd8) ? c c (#xx:3 of @rd16) ? c c (#xx:3 of @aa:8) ? c c (#xx:3 of rd8) ? c c (#xx:3 of @rd16) ? c c (#xx:3 of @aa:8) ? c c (#xx:3 of rd8) ? c c (#xx:3 of @rd16) ? c c (#xx:3 of @aa:8) ? c c ? (#xx:3 of rd8) ? c c ? (#xx:3 of @rd16) ? c c ? (#xx:3 of @aa:8) ? c c ? (#xx:3 of rd8) ? c b b b b b b b b b b b b b b b b b b b b b b b b b b b b 2 2 2 2 2 2 2 2 2 2 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2 6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ^ ^ ^ ^ ^ ^ rev. 3.0, 09/98, page 303 of 361 table a.1 instruction set (cont) mnemonic operation addressing mode/ instruction length operand size #xx: 8/16 rn @rn @(d:16, rn) @Crn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states ihnzvc condition code ? bixor #xx:3, @rd bixor #xx:3, @aa:8 bra d:8 (bt d:8) brn d:8 (bf d:8) bhi d:8 bls d:8 bcc d:8 (bhs d:8) bcs d:8 (blo d:8) bne d:8 beq d:8 bvc d:8 bvs d:8 bpl d:8 bmi d:8 bge d:8 blt d:8 bgt d:8 ble d:8 jmp @rn jmp @aa:16 jmp @@aa:8 bsr d:8 jsr @rn jsr @aa:16 c ? (#xx:3 of @rd16) ? c c ? (#xx:3 of @aa:8) ? c pc ? pc+d:8 pc ? pc+2 if condition is true then pc ? pc+d:8 else next; b b 4 2 2 4 4 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 6 6 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 6 8 6 6 8 c z = 0 c z = 1 c = 0 c = 1 z = 0 z = 1 v = 0 v = 1 n = 0 n = 1 n ? v = 0 n ? v = 1 z (n ? v) = 0 z (n ? v) = 1 pc ? rn16 pc ? aa:16 pc ? @aa:8 spC2 ? sp pc ? @sp pc ? pc+d:8 spC2 ? sp pc ? @sp pc ? rn16 spC2 ? sp pc ? @sp pc ? aa:16 ? branching condition rev. 3.0, 09/98, page 304 of 361 table a.1 instruction set (cont) mnemonic operation addressing mode/ instruction length (bytes) operand size #xx: 8/16 rn @rn @(d:16, rn) @Crn/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states ihnzvc condition code jsr @@aa:8 rts rte sleep ldc #xx:8, ccr ldc rs, ccr stc ccr, rd andc #xx:8, ccr orc #xx:8, ccr xorc #xx:8, ccr nop spC2 ? sp pc ? @sp pc ? @aa:8 pc ? @sp sp+2 ? sp ccr ? @sp sp+2 ? sp pc ? @sp sp+2 ? sp transit to sleep mode. #xx:8 ? ccr rs8 ? ccr ccr ? rd8 ccr #xx:8 ? ccr ccr #xx:8 ? ccr ccr ? #xx:8 ? ccr pc ? pc+2 b b b b b b 2 8 8 10 2 2 2 2 2 2 2 2 2 ? ? 2 ? ? ? ? 2 ? ? 2 ? ? ? ? ? ? 2 ? ? ? ? 2 ? ? 2 ? ? ? ? ? ? 2 ? ? ? ? ? ? 2 ? ? ? ? 2 the number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. (1) (2) (3) (4) (5) (6) (7) set to "1" when there is a carry or borrow from bit 11; otherwise cleared to "0." if the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to "0." set to "1" if decimal adjustment produces a carry; otherwise cleared to "0." the number of states required for execution is 4n+8 (n = value of r4l) these instructions are not supported by the h8/338 series. set to "1" if the divisor is negative; otherwise cleared to "0." cleared to "0" if the divisor is not zero; undetermined when the divisor is zero. notes: rev. 3.0, 09/98, page 305 of 361 a.2 operation code map table a.2 is a map of the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). some pairs of instructions have identical first bytes. these instructions are differentiated by the first bit of the second byte (bit 7 of the first instruction word). instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. instruction when first bit of byte 2 (bit 7 of first instruction word) is 1. rev. 3.0, 09/98, page 306 of 361 table a.2 operation code map high low 0123456789abcdef 0 1 2 3 4 5 6 7 8 9 a b c d e f nop bra mulxu bset shll shal sleep brn divxu bnot shlr shar stc bhi bclr rotxl rotl ldc bls btst rotxr rotr orc or bcc rts xorc xor bcs bsr bor bior bxor bixor band biand andc and bne rte ldc beq not neg bld bild bst bist add sub bvc bvs mov inc dec bpl jmp adds subs bmi eepmov mov cmp bge blt addx subx bgt jsr daa das ble mov add addx cmp subx or xor and mov mov * note: bit-manipulation instructions the push and pop instructions are identical in machine language to mov instructions. * rev. 3.0, 09/98, page 307 of 361 a.3 number of states required for execution the tables below can be used to calculate the number of states required for instruction execution. table a.3 indicates the number of states required for each cycle (instruction fetch, branch address read, stack operation, byte data access, word data access, internal operation). table a.4 indicates the number of cycles of each type occurring in each instruction. the total number of states required for execution of an instruction can be calculated from these two tables as follows: execution states = i s i + j s j + k s k + l s l + m s m + n s n examples: mode 1 (on-chip rom disabled), stack located in external memory, 1 wait state inserted in external memory access. 1. bset #0, @ffc7 from table a.4: i = l = 2, j = k = m = n= 0 from table a.3: s i = 8, s l = 3 number of states required for execution: 2 8 + 2 3 =22 2. jsr @@30 from table a.4: i = 2, j = k = 1, l = m = n = 0 from table a.3: s i = s j = s k = 8 number of states required for execution: 2 8 + 1 8 + 1 8 = 32 table a.3 number of states taken by each cycle in instruction execution access location execution status (instruction cycle) on-chip memory on-chip reg. field external memory instruction fetch s i branch address read s j stack operation s k 66 + 2m byte data access s l 33 + m word data access s m 2 66 + 2m internal operation s n 1 notes: m: number of wait states inserted in access to external device. rev. 3.0, 09/98, page 308 of 361 table a.4 number of cycles in each instruction instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n add add.b #xx:8, rd add.b rs, rd add.w rs, rd 1 1 1 adds adds.w #1/2, rd 1 addx addx.b #xx:8, rd addx.b rs, rd 1 1 and and.b #xx:8, rd and.b rs, rd 1 1 andc andc #xx:8, ccr 1 band band #xx:3, rd band #xx:3, @rd band #xx:3, @aa:8 1 2 2 1 1 bcc bra d:8 (bt d:8) brn d:8 (bf d:8) bhi d:8 bls d:8 bcc d:8 (bhs d:8) bcs d:8 (blo d:8) bne d:8 beq d:8 bvc d:8 bvs d:8 bpl d:8 bmi d:8 bge d:8 blt d:8 bgt d:8 ble d:8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 bclr bclr #xx:3, rd bclr #xx:3, @rd bclr #xx:3, @aa:8 bclr rn, rd bclr rn, @rd bclr rn, @aa:8 1 2 2 1 2 2 2 2 2 2 note: all values left blank are zero. rev. 3.0, 09/98, page 309 of 361 table a.4 number of cycles in each instruction (cont) instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n biand biand #xx:3, rd biand #xx:3, @rd biand #xx:3, @aa:8 1 2 2 1 1 bild bild #xx:3, rd bild #xx:3, @rd bild #xx:3, @aa:8 1 2 2 1 1 bior bior #xx:3, rd bior #xx:3, @rd bior #xx:3, @aa:8 1 2 2 1 1 bist bist #xx:3, rd bist #xx:3, @rd bist #xx:3, @aa:8 1 2 2 2 2 bixor bixor #xx:3, rd bixor #xx:3, @rd bixor #xx:3, @aa:8 1 2 2 1 1 bld bld #xx:3, rd bld #xx:3, @rd bld #xx:3, @aa:8 1 2 2 1 1 bnot bnot #xx:3, rd bnot #xx:3, @rd bnot #xx:3, @aa:8 bnot rn, rd bnot rn, @rd bnot rn, @aa:8 1 2 2 1 2 2 2 2 2 2 bor bor #xx:3, rd bor #xx:3, @rd bor #xx:3, @aa:8 1 2 2 1 1 bset bset #xx:3, rd bset #xx:3, @rd bset #xx:3, @aa:8 bset rn, rd bset rn, @rd bset rn, @aa:8 1 2 2 1 2 2 2 2 2 2 note: all values left blank are zero. rev. 3.0, 09/98, page 310 of 361 table a.4 number of cycles in each instruction (cont) instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n bsr bsr d:8 2 1 bst bst #xx:3, rd bst #xx:3, @rd bst #xx:3, @aa:8 1 2 2 2 2 btst btst #xx:3, rd btst #xx:3, @rd btst #xx:3, @aa:8 btst rn, rd btst rn, @rd btst rn, @aa:8 1 2 2 1 2 2 1 1 1 1 bxor bxor #xx:3, rd bxor #xx:3, @rd bxor #xx:3, @aa:8 1 2 2 1 1 cmp cmp.b #xx:8, rd cmp.b rs, rd cmp.w rs, rd 1 1 1 daa daa.b rd 1 das das.b rd 1 dec dec.b rd 1 divxu divxu.b rs, rd 1 12 eepmov eepmov 2 2n+2 * 1 inc inc.b rd 1 jmp jmp @rn jmp @aa:16 jmp @@aa:8 2 2 21 2 2 jsr jsr @rn jsr @aa:16 jsr @@aa:8 2 2 21 1 1 1 2 ldc ldc #xx:8, ccr ldc rs, ccr 1 1 mov mov.b #xx:8, rd mov.b rs, rd mov.b @rs, rd mov.b @(d:16,rs), rd 1 1 1 2 1 1 notes: all values left blank are zero. * n: initial value in r4l. source and destination are accessed n + 1 times each. rev. 3.0, 09/98, page 311 of 361 table a.4 number of cycles in each instruction (cont) instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n mov mov.b @rs+, rd 1 1 2 mov.b @aa:8, rd 1 1 mov.b @aa:16, rd 2 1 mov.b rs, @rd 1 1 mov.b rs, @(d:16, rd) 21 mov.b rs, @-rd 1 1 2 mov.b rs, @aa:8 1 1 mov.b rs, @aa:16 2 1 mov.w #xx:16, rd 2 mov.w rs, rd 1 mov.w @rs, rd 1 1 mov.w @(d:16, rs), rd 21 mov.w @rs+, rd 1 1 2 mov.w @aa:16, rd 2 1 mov.w rs, @rd 1 1 mov.w rs, @(d:16, rd) 21 mov.w rs, @-rd 1 1 2 mov.w rs, @aa:16 2 1 movfpe movfpe @aa:16, rd not supported movtpe movtpe.rs, @aa:16 not supported mulxu mulxu.rs, rd 1 12 neg neg.b rd 1 nop nop 1 not not.b rd 1 or or.b #xx:8, rd 1 or.b rs, rd 1 orc orc #xx:8, ccr 1 pop pop rd 1 1 2 push push rs 1 1 2 rotl rotl.b rd 1 rotr rotr.b rd 1 rotxl rotxl.b rd 1 rotxr rotxr.b rd 1 rte rte 2 2 2 rts rts 2 1 2 note: all values left blank are zero. rev. 3.0, 09/98, page 312 of 361 table a.4 number of cycles in each instruction (cont) instruction mnemonic instruction fetch i branch addr. read j stack operation k byte data access l word data access m internal operation n shal shal.b rd 1 shar shar.b rd 1 shll shll.b rd 1 shlr shlr.b rd 1 sleep sleep 1 stc stc ccr, rd 1 sub sub.b rs, rd sub.w rs, rd 1 1 subs subs.w #1/2, rd 1 subx subx.b #xx:8, rd subx.b rs, rd 1 1 xor xor.b #xx:8, rd xor.b rs, rd 1 1 xorc xorc #xx:8, ccr 1 note: all values left blank are zero. rev. 3.0, 09/98, page 313 of 361 appendix b register field b.1 register addresses and bit names bit names addr. (last byte) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'80 h'81 h'82 h'83 h'84 h'85 h'86 h'87 external addresses (in expanded modes) h'88 smr c/ a chr pe o/ e stop mp cks1 cks0 h'89 brr h'8a scr tie rie te re mpie teie cke1 cke0 h'8b tdr h'8c ssr tdre rdrf orer fer per tend mpb mpbt h'8d rdr h'8e h'8f sci1 h'90 tier iciae icibe icice icide ociae ocibe ovie ? h'91 tcsr icfa icfb icfc icfd ocfa ocfb ovf cclra h'92 frc (h) h'93 frc (l) h'94 ocra (h) ocrb (h) h'95 ocra (l) ocrb (l) h'96 tcr iedga iedgb iedgc iedgd bufea bufeb cks1 cks0 h'97 tocr ??? ocrs oea oeb olvla olvlb h'98 icra (h) h'99 icra (l) h'9a icrb (h) h'9b icrb (l) h'9c icrc (h) frt h'9d icrc (l) h'9e icrd (h) h'9f icrd (l) notes: frt: free-running timer sci1: serial communication interface 1 rev. 3.0, 09/98, page 314 of 361 bit names addr. (last byte) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'a0 tcr oe os ??? cks2 cks1 cks0 pwm0 h'a1 dtr h'a2 tcnt h'a3 ? ???????? h'a4 tcr oe os ??? cks2 cks1 cks0 pwm1 h'a5 dtr h'a6 tcnt h'a7 ? ???????? h'a8 dadr0 d/a h'a9 dadr1 h'aa dacr daoe1 daoe0 dae ????? h'ab ? ???????? h'ac p1pcr p1 7 pcr p1 6 pcr p1 5 pcr p1 4 pcr p1 3 pcr p1 2 pcr p1 1 pcr p1 0 pcr port 1 h'ad p2pcr p2 7 pcr p2 6 pcr p2 5 pcr p2 4 pcr p2 3 pcr p2 2 pcr p2 1 pcr p2 0 pcr port 2 h'ae p3pcr p3 7 pcr p3 6 pcr p3 5 pcr p3 4 pcr p3 3 pcr p3 2 pcr p3 1 pcr p3 0 pcr port 3 h'af ? ????????? h'b0 p1ddr p1 7 ddr p1 6 ddr p1 5 ddr p1 4 ddr p1 3 ddr p1 2 ddr p1 1 ddr p1 0 ddr port 1 h'b1 p2ddr p2 7 ddr p2 6 ddr p2 5 ddr p2 4 ddr p2 3 ddr p2 2 ddr p2 1 ddr p2 0 ddr port 2 h'b2 p1dr p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 port 1 h'b3 p2dr p2 7 p2 6 p2 5 p2 4 p2 3 p2 2 p2 1 p2 0 port 2 h'b4 p3ddr p3 7 ddr p3 6 ddr p3 5 ddr p3 4 ddr p3 3 ddr p3 2 ddr p3 1 ddr p3 0 ddr port 3 h'b5 p4ddr p4 7 ddr p4 6 ddr p4 5 ddr p4 4 ddr p4 3 ddr p4 2 ddr p4 1 ddr p4 0 ddr port 4 h'b6 p3dr p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 port 3 h'b7 p4dr p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 port 4 h'b8 p5ddr ????? p5 2 ddr p5 1 ddr p5 0 ddr port 5 h'b9 p6ddr p6 7 ddr p6 6 ddr p6 5 ddr p6 4 ddr p6 3 ddr p6 2 ddr p6 1 ddr p6 0 ddr port 6 h'ba p5dr ????? p5 2 p5 1 p5 0 port 5 h'bb p6dr p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 port 6 h'bc ? ????????? h'bd p8ddr ? p8 6 ddr p8 5 ddr p8 4 ddr p8 3 ddr p8 2 ddr p8 1 ddr p8 0 ddr port 8 h'be p7dr p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 port 7 h'bf p8dr ? p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 port 8 notes: pwm0: pulse-width modulation timer channel 0 pwm1: pulse-width modulation timer channel 1 d/a: d/a converter rev. 3.0, 09/98, page 315 of 361 bit names addr. (last byte) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'c0 p9ddr p9 7 ddr p9 6 ddr p9 5 ddr p9 4 ddr p9 3 ddr p9 2 ddr p9 1 ddr p9 0 ddr port 9 h'c1 p9dr p9 7 p9 6 p9 5 p9 4 p9 3 p9 2 p9 1 p9 0 h'c2 ? ???????? h'c3 stcr ????? mpe icks1 icks0 h'c4 syscr ssby sts2 sts1 sts0 ? nmieg dpme rame h'c5 mdcr ?????? mds1 mds0 h'c6 iscr irq 7 sc irq 6 sc irq 5 sc irq 4 sc irq 3 sc irq 2 sc irq 1 sc irq 0 sc h'c7 ier irq 7 eirq 6 eirq 5 eirq 4 eirq 3 eirq 2 eirq 1 eirq 0 e system control h'c8 tcr cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr0 h'c9 tcsr cmfb cmfa ovf ? os3 os2 os1 os0 h'ca tcora h'cb tcorb h'cc tcnt h'cd ? ???????? h'ce ? ???????? h'cf ? ???????? h'd0 tcr cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 tmr1 h'd1 tcsr cmfb cmfa ovf ? os3 os2 os1 os0 h'd2 tcora h'd3 tcorb h'd4 tcnt h'd5 ? ???????? h'd6 ? ???????? h'd7 ? ???????? h'd8 smr c/ a chr pe o/ e stop mp cks1 cks0 sci0 h'd9 brr h'da scr tie rie te re mpie teie cke1 cke0 h'db tdr h'dc ssr tdre rdrf orer fer per tend mpb mpbt h'dd rdr h'de ? ???????? h'df ? ???????? notes: tmr0: 8-bit timer channel 0 tmr1: 8-bit timer channel 1 sci0: serial communication interface 0 rev. 3.0, 09/98, page 316 of 361 bit names addr. (last byte) register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'e0 addra a/d h'e1 ? ???????? h'e2 addrb h'e3 ? ???????? h'e4 addrc h'e5 ? ???????? h'e6 addrd h'e7 ? ???????? h'e8 adcsr adf adie adst scan cks ch2 ch1 ch0 h'e9 ? ???????? h'ea adcr trge ?????? chs h'eb ? ???????? h'ec ? ????????? h'ed ? ???????? h'ee ? ???????? h'ef ? ???????? h'f0 ? ????????? h'f1 ? ???????? h'f2 ? ???????? h'f3 ? ???????? h'f4 ? ???????? h'f5 ? ???????? h'f6 ? ???????? h'f7 ? ???????? h'f8 ? ???????? h'f9 ? ???????? h'fa ? ???????? h'fb ? ???????? h'fc ? ???????? h'fd ? ???????? h'fe ? ???????? h'ff ? ???????? note: a/d: analog-to-digital converter rev. 3.0, 09/98, page 317 of 361 b.2 register descriptions 7 iciae 0 r/w bit initial value read/write 6 icibe 0 r/w 5 icice 0 r/w 4 icide 0 r/w overflow interrupt enable overflow interrupt request is enabled. overflow interrupt request is disabled. 1 0 output compare interrupt b enable output compare interrupt request b is enabled. output compare interrupt request b is disabled. 1 0 output compare interrupt a enable output compare interrupt request a is enabled. output compare interrupt request a is disabled. 1 0 input capture interrupt d enable input capture interrupt request d is enabled. input capture interrupt request d is disabled. 1 0 3 ociae 0 r/w 2 ocibe 0 r/w 1 ovie 0 r/w 0 1 tiertimer interrupt enable register h'ff90 frt bit no. initial value type of access permitted r w r/w abbreviation of register name register name address onto which register is mapped name of on-chip supporting module bit names (abbreviations). bits marked are reserved. full name of bit description of bit function read only write only read or write rev. 3.0, 09/98, page 318 of 361 smr ? serial mode register h'ff88 sci1 bit initial value read/write 7 c/a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w 4 o/e 0 r/w clock select 0 0 1 1 1 ? clock ?/4 clock 0 ?/16 clock ?/64 clock multiprocessor mode 0 multiprocessor function disabled 1 multiprocessor format selected stop bit length 0 one stop bit 1 two stop bits parity mode 0 even parity 1 odd parity parity enable 0 transmit: no parity bit added. receive: parity bit not checked. 1 transmit: no parity bit added. receive: parity bit not checked. character length 0 8-bit data length 1 7-bit data length communication mode 0 asynchronous 1 synchronous 3 stop 0 r/w rev. 3.0, 09/98, page 319 of 361 brr ? bit rate register h'ff89 sci1 bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w constant that determines the bit rate rev. 3.0, 09/98, page 320 of 361 scr ? serial control register h'ff8a sci1 bit initial value read/write 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 1 r/w 2 teie 0 r/w 1 cke1 0 r/w clock enable 0 0 asynchronous serial clock not output asynchronous serial clock output at sck pin 1 clock enable 0 internal clock external clock 1 transmit end interrupt enable 0 tsr-empty interrupt request is disabled. tsr-empty interrupt request is enabled. 1 multiprocessor interrupt enable 0 multiprocessor receive interrupt function is disabled. multiprocessor receive interrupt function is enabled. 1 receive enable 0 receive disabled receive enabled 1 transmit enable 0 transmit disabled transmit enabled 1 receive interrupt enable 0 receive interrupt and receive error interrupt requests are disabled. receive interrupt and receive error interrupt requests are enabled. 1 transmit interrupt enable 0 tdr-empty interrupt request is disabled. tdr-empty interrupt request is enabled. 1 rev. 3.0, 09/98, page 321 of 361 tdr ? transmit data register h'ff8b sci1 bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w transmit data rev. 3.0, 09/98, page 322 of 361 ssr ? serial status register h'ff8c sci1 bit initial value read/write note: * software can write a 0 in bits 7 to 3 to clear the flags, but cannot write a 1 in these bits. 7 tdre 1 r/(w) 6 rdrf 0 r/(w) 5 orer 0 r/(w) 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r 4 fer 0 r/(w) receive data register full 0 cleared when cpu reads rdrf = 1, then writes 0 in rdrf. 1 set when one character is received normally and transferred from rsr to rdr. transmit data register empty 0 cleared when cpu reads tdre = 1, then writes 0 in tdre. 1 set when: 1. data is transferred from tdr to tsr. 2. te is cleared while tdre = 0. transmit end 0 cleared when cpu reads tdre = 1, then writes 0 in tdre. 1 set to 1 when te = 0, or when tdre = 1 at the end of character transmission. parity error 0 cleared when cpu reads per = 1, then writes 0 in per. 1 set when a parity error occurs (parity of receive data does not match parity selected by o/e bit in smr). framing error 0 cleared when cpu reads fer = 1, then writes 0 in fer. 1 set when a framing error occurs (stop bit is 0). overrun error 0 cleared when cpu reads orer = 1, then writes 0 in orer. 1 set when an overrun error occurs (next data is completely received while rdrf bit is set to 1). multiprocessor bit multiprocessor bit transfer 0 multiprocessor bit = 0 in receive data. 1 multiprocessor bit = 1 in receive data. 0 multiprocessor bit = 0 in transmit data. 1 multiprocessor bit = 1 in transmit data. 3 per 0 r/(w) ***** rev. 3.0, 09/98, page 323 of 361 rdr ? receive data register h'ff8d sci1 bit initial value read/write 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r receive data rev. 3.0, 09/98, page 324 of 361 tier ? timer interrupt enable register h'ff90 frt bit initial value read/write 7 iciae 0 r/w 6 icibe 0 r/w 5 icice 0 r/w 4 icide 0 r/w 3 ociae 0 r/w 0 1 2 ocibe 0 r/w 1 ovie 0 r/w overflow interrupt enable 0 overflow interrupt request is disabled. overflow interrupt request is enabled. 1 output compare interrupt b enable 0 output compare interrupt request b is disabled. output compare interrupt request b is enabled. 1 output compare interrupt a enable 0 output compare interrupt request a is disabled. output compare interrupt request a is enabled. 1 input capture interrupt d enable 0 input capture interrupt request d is disabled. input capture interrupt request d is enabled. 1 input capture interrupt c enable 0 input capture interrupt request c is disabled. input capture interrupt request c is enabled. 1 input capture interrupt b enable 0 input capture interrupt request b is disabled. input capture interrupt request b is enabled. 1 input capture interrupt a enable 0 input capture interrupt request a is disabled. input capture interrupt request a is enabled. 1 rev. 3.0, 09/98, page 325 of 361 tcsr ? timer control/status register h'ff91 frt bit initial value read/write 7 icfa 0 r/(w) 6 icfb 0 r/(w) 5 icfc 0 r/(w) 4 icfd 0 r/(w) 3 ocfa 0 r/(w) 0 cclra 0 r/w 2 ocfb 0 r/(w) 1 ovf 0 r/(w) ******* 0 0 cleared when cpu reads ovf = "1," then writes "0" in ovf. timer overflow 1 set when frc changes from h'ffff to h'0000. 0 cleared when cpu reads ocfb = "1", then writes "0" in ocfb. 1 set when frc = ocrb. 0 cleared when cpu reads ocfa = "1", then writes "0" in ocfa. 1 set when frc = ocra. 0 cleared when cpu reads icfd = "1", then writes "0" in icfd. 1 set by ftid input. 0 cleared when cpu reads icfc = "1", then writes "0" in icfc. 1 set by ftid input. 0 0 cleared when cpu reads icfb = "1", then writes "0" in icfb. 1 set when ftib input causes frc to be copied to icrb. 0 cleared when cpu reads icfa = "1", then writes "0" in icfa. 1 set when ftia input causes frc to be copied to icra. 0 frc count is not cleared. frc count is cleared by compare-match a. counter clear a 1 output compare flag b output compare flag a input capture flag d input capture flag c input capture flag b input capture flag a note: * software can write a "0" in bits 7 to 1 to clear the flags, but cannot write a "1" in these bits. rev. 3.0, 09/98, page 326 of 361 frc (h and l) ? free-running counter h'ff92, h'ff93 frt bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w count value ocra (h and l) ? output compare register a h'ff94, h'ff95 frt bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w continually compared with frc. ocfa is set to 1 when ocra=frc. ocrb (h and l) ? output compare register b h'ff94, h'ff95 frt bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w continually compared with frc. ocfb is set to ??when ocrb=frc. rev. 3.0, 09/98, page 327 of 361 tcr ? timer control register h'ff96 frt bit initial value read/write 7 iedga 0 r/w 6 iedgb 0 r/w 5 iedgc 0 r/w 4 iedgd 0 r/w 3 bufea 0 r/w 0 cks0 0 r/w 2 bufeb 0 r/w 1 cks1 0 r/w clock enable 0 0 0 internal clock source: ?/2 1 internal clock source: ?/8 0 internal clock source: ?/32 1 external clock source: counted on rising edge 1 1 1 buffer enable b 0 icrd is used for input capture d. icrd is buffer register for input capture b. 1 input edge select d 0 falling edge of ftid is valid. rising edge of ftid is valid. 1 buffer enable a 0 icrc is used for input capture c. icrc is buffer register for input capture a. 1 input edge select c 0 falling edge of ftic is valid. rising edge of ftic is valid. 1 input edge select b 0 falling edge of ftib is valid. rising edge of ftib is valid. 1 input edge select a 0 falling edge of ftia is valid. rising edge of ftia is valid. 1 rev. 3.0, 09/98, page 328 of 361 tocr ? timer output compare control register h'ff97 frt bit initial value read/write 7 1 6 1 5 1 4 ocrs 0 r/w 3 oea 0 r/w 0 olvlb 0 r/w 2 oeb 0 r/w 1 olvla 0 r/w output level a 0 compare-match a causes 0 output. compare-match a causes 1 output. 1 output level b 0 compare-match b causes 0 output. compare-match b causes 1 output. 1 output enable a 0 output compare a output is disabled. output compare a output is enabled. 1 output enable b 0 output compare b output is disabled. output compare b output is enabled. 1 output compare register select 0 the cpu can access ocra. the cpu can access ocrb. 1 icra (h and l) ? input capture register a h'ff98, h'ff99 frt bit initial value read/write 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r contains frc count captured on ftia input. rev. 3.0, 09/98, page 329 of 361 icrb (h and l) ? input capture register b h'ff9a, h'ff9b frt bit initial value read/write 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r contains frc count captured on ftib input. icrc (h and l) ? input capture register c h'ff9c, h'ff9d frt bit initial value read/write 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r contains frc count captured on ftic input, or old icra value in buffer mode. icrd (h and l) ? input capture register d h'ff9e, h'ff9f frt bit initial value read/write 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r contains frc count captured on ftid input, or old icrb value in buffer mode. rev. 3.0, 09/98, page 330 of 361 tcr ? timer control register h'ffa0 pwm0 bit initial value read/write 7 oe 0 r/w 6 os 0 r/w 5 1 4 1 3 1 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w clock select (values when ?= 10 mhz) ?/2 200ns 50s 20khz ?/8 800ns 200s 5khz ?/32 3.2s 800s 1.25khz ?/128 12.8s 3.2ms 312.5hz ?/256 25.6s 6.4ms 156.3hz ?/1024 102.4s 25.6ms 39.1hz ?/2048 204.8s 51.2ms 19.5hz ?/4096 409.6s 102.4ms 9.8hz internal clock freq. reso- lution pwm period pwm frequency 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 output select 0 positive logic negative logic 1 output enable 0 pwm output disabled; tcnt cleared to h'00 and stops. pwm output enabled; tcnt runs. 1 dtr ? duty register h'ffa1 pwm0 bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w pulse duty cycle rev. 3.0, 09/98, page 331 of 361 tcnt ? timer counter h'ffa2 pwm0 bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w count value (runs from h'00 to h'f9, then repeats from h'00) tcr ? timer control register h'ffa4 pwm1 bit initial value read/write 7 oe 0 r/w 6 ow 0 r/w 5 1 4 1 3 1 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w note: bit functions are the same as for pwm0. dtr ? duty register h'ffa5 pwm1 bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w note: bit functions are the same as for pwm0. rev. 3.0, 09/98, page 332 of 361 tcnt ? timer counter h'ffa6 pwm1 bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w note: bit functions are the same as for pwm0. dadr0 ? d/a data register 0 h'ffa8 d/a bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w data to be converted dadr1 ? d/a data register 1 h'ffa9 d/a bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w data to be converted rev. 3.0, 09/98, page 333 of 361 dacr ? d/a control register h'ffaa d/a bit initial value read/write 7 daoe1 0 r/w 6 daoe0 0 r/w 5 dae 0 r/w 4 1 3 1 0 1 2 1 1 1 daoe1 daoe0 dae d/a analog output 0 0 0 channels 0 and 1 disabled. 0 1 0 channel 0 disabled, channel 1 enabled. 0 1 1 channels 0 and 1 enabled. 1 0 0 channel 0 enabled, channel 1 disabled. 1 0 1 channels 0 and 1 enabled. 1 1 channels 0 and 1 enabled. p1pcr ? port 1 input pull-up control register h'ffac port 1 bit initial value read/write 7 p1 7 pcr 0 r/w 6 p1 6 pcr 0 r/w 5 p1 5 pcr 0 r/w 4 p1 4 pcr 0 r/w 3 p1 3 pcr 0 r/w 0 p1 0 pcr 0 r/w 2 p1 2 pcr 0 r/w 1 p1 1 pcr 0 r/w port 1 input pull-up control input pull-up transistor is off. input pull-up transistor is on. 1 2 rev. 3.0, 09/98, page 334 of 361 p2pcr ? port 2 input pull-up control register h'ffad port 2 bit initial value read/write 7 p2 7 pcr 0 r/w 6 p2 6 pcr 0 r/w 5 p2 5 pcr 0 r/w 4 p2 4 pcr 0 r/w 3 p2 3 pcr 0 r/w 0 p2 0 pcr 0 r/w 2 p2 2 pcr 0 r/w 1 p2 1 pcr 0 r/w port 2 input pull-up control input pull-up transistor is off. input pull-up transistor is on. 0 1 p3pcr ? port 3 input pull-up control register h'ffae port 3 bit initial value read/write 7 p3 7 pcr 0 r/w 6 p3 6 pcr 0 r/w 5 p3 5 pcr 0 r/w 4 p3 4 pcr 0 r/w 3 p3 3 pcr 0 r/w 0 p3 0 pcr 0 r/w 2 p3 2 pcr 0 r/w 1 p3 1 pcr 0 r/w port 3 input pull-up control input pull-up transistor is off. input pull-up transistor is on. 0 1 rev. 3.0, 09/98, page 335 of 361 p1ddr ? port 1 data direction register h'ffb0 port 1 bit mode 1 initial value read/write modes 2 and 3 initial value read/write 7 p1 7 ddr 1 0 w 6 p1 6 ddr 1 0 w 5 p1 5 ddr 1 0 w 4 p1 4 ddr 1 0 w 3 p1 3 ddr 1 0 w 0 p1 0 ddr 1 0 w 2 p1 2 ddr 1 0 w 1 p1 1 ddr 1 0 w port 4 input/output control input port output port 0 1 p1dr ? port 1 data register h'ffb2 port 1 bit initial value read/write 7 p1 7 0 r/w 6 p1 6 0 r/w 5 p1 5 0 r/w 4 p1 4 0 r/w 3 p1 3 0 r/w 0 p1 0 0 r/w 2 p1 2 0 r/w 1 p1 1 0 r/w rev. 3.0, 09/98, page 336 of 361 p2ddr ? port 2 data direction register h'ffb1 port 2 bit mode 1 initial value read/write modes 2 and 3 initial value read/write 7 p2 7 ddr 1 0 w 6 p2 6 ddr 1 0 w 5 p2 5 ddr 1 0 w 4 p2 4 ddr 1 0 w 3 p2 3 ddr 1 0 w 0 p2 0 ddr 1 0 w 2 p2 2 ddr 1 0 w 1 p2 1 ddr 1 0 w port 2 input/output control input port output port 0 1 p2dr ? port 2 data register h'ffb3 port 2 bit initial value read/write 7 p2 7 0 r/w 6 p2 6 0 r/w 5 p2 5 0 r/w 4 p2 4 0 r/w 3 p2 3 0 r/w 0 p2 0 0 r/w 2 p2 2 0 r/w 1 p2 1 0 r/w p3ddr ? port 3 data direction register h'ffb4 port 3 bit initial value read/write 7 p3 7 ddr 0 w 6 p3 6 ddr 0 w 5 p3 5 ddr 0 w 4 p3 4 ddr 0 w 3 p3 3 ddr 0 w 0 p3 0 ddr 0 w 2 p3 2 ddr 0 w 1 p3 1 ddr 0 w port 3 input/output control input port output port 0 1 rev. 3.0, 09/98, page 337 of 361 p3dr ? port 3 data register h'ffb6 port 3 bit initial value read/write 7 p3 7 0 r/w 6 p3 6 0 r/w 5 p3 5 0 r/w 4 p3 4 0 r/w 3 p3 3 0 r/w 0 p3 0 0 r/w 2 p3 2 0 r/w 1 p3 1 0 r/w p4ddr ? port 4 data direction register h'ffb5 port 4 bit initial value read/write 7 p4 7 ddr 0 w 6 p4 6 ddr 0 w 5 p4 5 ddr 0 w 4 p4 4 ddr 0 w 3 p4 3 ddr 0 w 0 p4 0 ddr 0 w 2 p4 2 ddr 0 w 1 p4 1 ddr 0 w port 4 input/output control input port output port 0 1 p4dr ? port 4 data register h'ffb7 port 4 bit initial value read/write 7 p4 7 0 r/w 6 p4 6 0 r/w 5 p4 5 0 r/w 4 p4 4 0 r/w 3 p4 3 0 r/w 0 p4 0 0 r/w 2 p4 2 0 r/w 1 p4 1 0 r/w p5ddr ? port 5 data direction register h'ffb8 port 5 bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 p5 0 ddr 0 w 2 p5 2 ddr 0 w 1 p5 1 ddr 0 w port 5 input/output control input port output port 0 1 rev. 3.0, 09/98, page 338 of 361 p5dr ? port 5 data register h'ffba port 5 bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 p5 0 0 r/w 2 p5 2 0 r/w 1 p5 1 0 r/w p6ddr ? port 6 data direction register h'ffb9 port 6 bit initial value read/write 7 p6 7 ddr 0 w 6 p6 6 ddr 0 w 5 p6 5 ddr 0 w 4 p6 4 ddr 0 w 3 p6 3 ddr 0 w 0 p6 0 ddr 0 w 2 p6 2 ddr 0 w 1 p6 1 ddr 0 w port 6 input/output control input port output port 0 1 p6dr ? port 6 data register h'ffbb port 6 bit initial value read/write 7 p6 7 0 r/w 6 p6 6 0 r/w 5 p6 5 0 r/w 4 p6 4 0 r/w 3 p6 3 0 r/w 0 p6 0 0 r/w 2 p6 2 0 r/w 1 p6 1 0 r/w p7dr ? port 7 data register h'ffbe port 7 bit initial value read/write note: * depends on the levels of pins p7 7 to p7 0 . 7 p7 7 * r 6 p7 6 * r 5 p7 5 * r 4 p7 4 * r 3 p7 3 * r 0 p7 0 * r 2 p7 2 * r 1 p7 1 * r rev. 3.0, 09/98, page 339 of 361 p8ddr ? port 8 data direction register h'ffbd port 8 bit initial value read/write 7 1 6 p8 6 ddr 0 w 5 p8 5 ddr 0 w 4 p8 4 ddr 0 w 3 p8 3 ddr 0 w 0 p8 0 ddr 0 w 2 p8 2 ddr 0 w 1 p8 1 ddr 0 w port 8 input/output control input port output port 0 1 p8dr ? port 8 data register h'ffbf port 8 bit initial value read/write 7 1 6 p8 6 0 r/w 5 p8 5 0 r/w 4 p8 4 0 r/w 3 p8 3 0 r/w 0 p8 0 0 r/w 2 p8 2 0 r/w 1 p8 1 0 r/w p9ddr ? port 9 data direction register h'ffc0 port 9 bit mode 1 and 2 initial value read/write mode 3 initial value read/write 7 p9 7 ddr 0 w 0 w 6 p9 6 ddr 1 0 w 5 p9 5 ddr 0 w 0 w 4 p9 4 ddr 0 w 0 w 3 p9 3 ddr 0 w 0 w 0 p9 0 ddr 0 w 0 w 2 p9 2 ddr 0 w 0 w 1 p9 1 ddr 0 w 0 w port 9 input/output control input port output port 0 1 rev. 3.0, 09/98, page 340 of 361 p9dr ? port 9 data register h'ffc1 port 9 bit initial value read/write notes: * depends on the level of pin p9 6 . 7 p9 6 0 r/w 6 p9 6 * r 5 p9 5 0 r/w 4 p9 4 0 r/w 3 p9 3 0 r/w 0 p9 0 0 r/w 2 p9 2 0 r/w 1 p9 1 0 r/w stcr ? serial/timer control register h'ffc3 tmr0/1 bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 icks0 0 r/w 2 mpe 0 r/w 1 icks1 0 r/w multiprocessor enable multiprocessor communication function is disabled. multiprocessor communication function is enabled. 0 1 internal clock source select see tcr under tmr0 and tmr1. rev. 3.0, 09/98, page 341 of 361 syscr ? system control register h'ffc4 system control bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 1 0 rame 1 r/w 2 nmieg 0 r/w 1 dpme 0 r/w * dual-port ram enable not supported. (do not set to 1.) ram enable 0 on-chip ram is disabled. on-chip ram is enabled. 1 standby timer select 0 0 0 clock settling time = 8192 states 0 0 1 clock settling time = 16384 states 0 1 0 clock settling time = 32768 states 0 1 1 clock settling time = 65536 states 1 C C clock settling time = 131072 states nmi edge 0 falling edge of nmi is detected. rising edge of nmi is detected. 1 software standby 0 note: * do not set dpme to 1. sleep instruction causes transition to sleep mode. sleep instruction causes transition to software standby mode. 1 rev. 3.0, 09/98, page 342 of 361 mdcr ? mode control register h'ffc5 system control bit initial value read/write note: * determined by inputs at pins md 1 and md 0 7 1 6 1 5 1 4 0 3 0 0 mds 0 * r/w 2 1 1 mds 1 * r/w mode select bits value at mode pins. iscr ? irq sense control register h'ffc6 system control bit initial value read/write 7 irq 7 sc 0 r/w 6 irq 6 sc 0 r/w 5 irq 5 sc 0 r/w 4 irq 4 sc 0 r/w 3 irq 3 sc 0 r/w 0 irq 0 sc 0 r/w 2 irq 2 sc 0 r/w 1 irq 1 sc 0 r/w irq 0 to irq 7 sense control irqi is level-sensed (active low). irqi is edge-sensed (falling edge). 0 1 ier ? irq enable register h'ffc7 system control bit initial value read/write 7 irq 7 e 0 r/w 6 irq 6 e 0 r/w 5 irq 5 e 0 r/w 4 irq 4 e 0 r/w 3 irq 3 e 0 r/w 0 irq 0 e 0 r/w 2 irq 2 e 0 r/w 1 irq 1 e 0 r/w irq 0 to irq 7 enable irqi is disabled. irqi is enabled. 0 1 rev. 3.0, 09/98, page 343 of 361 tcr ? timer control register h'ffc8 tmr0 bit initial value read/write 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w clock select cks2 cks1 cks0 icks1 icks0 description 0 0 0 timer stopped 0 0 1 0 ?/8 internal clock, falling edge 0 0 1 1 ?/2 internal clock, falling edge 0 1 0 0 ?/64 internal clock, falling edge 0 1 0 1 ?/32 internal clock, falling edge 0 1 1 0 ?/1024 internal clock, falling edge 0 1 1 1 ?/256 internal clock, falling edge 1 0 0 timer stopped 1 0 1 external clock, rising edge 1 1 0 external clock, falling edge 1 1 1 external clock, rising and falling edges tcr stcr compare-match interrupt enable a 0 compare-match a interrupt request is disabled. compare-match a interrupt request is enabled. 1 compare-match interrupt enable b 0 compare-match b interrupt request is disabled. compare-match b interrupt request is enabled. counter clear 0 0 counter is not cleared. 0 1 cleared by compare-match a. 1 0 cleared by compare-match b. 1 1 cleared on rising edge of external reset input. timer overflow interrupt enable overflow interrupt request is disabled. overflow interrupt request is enabled. 0 1 1 rev. 3.0, 09/98, page 344 of 361 tcsr ? timer control/status register h'ffc9 tmr0 bit initial value read/write 7 cmfb 0 r/(w) * 1 6 cmfa 0 r/(w) * 1 5 ovf 0 r/(w) * 1 4 1 3 os3 * 2 0 r/w 0 os0 * 2 0 r/w 2 os2 * 2 0 r/w 1 os1 * 2 0 r/w output select 0 0 no change on compare-match a. 0 1 output ??on compare-match a. 1 0 output ??on compare-match a. 1 1 invert (toggle) output on compare-match a. output select 0 0 no change on compare-match b. 0 1 output ??on compare-match b. 1 0 output ??on compare-match b. 1 1 invert (toggle) output on compare-match b. compare-match flag a 0 notes: 1. 2. software can write a ??in bits 7 to 5 to clear the flags, but cannot write a ??in these bits. when all four bits (os3 to os0) are cleared to ?,?output is disabled. cleared when cpu reads cmfa = ?,?then writes ??in cmfa. set when tcnt = tcora. 1 compare-match flag b 0 cleared from when cpu reads cmfb = ?,?then writes ??in cmfb. set when tcnt = tcorb. 1 timer overflow flag 0 cleared when cpu reads ovf = ?,?then writes ??in ovf. set when tcnt changes from h'ff to h'00. 1 rev. 3.0, 09/98, page 345 of 361 tcora ? time constant register a h'ffca tmr0 bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w the cmfa bit is set to ??when tcora= tcnt. tcorb ? time constant register b h'ffcb tmr0 bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w the cmfb bit is set to ??when tcorb= tcnt. tcnt ? timer counter h'ffcc tmr0 bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w count value rev. 3.0, 09/98, page 346 of 361 tcr ? timer conrol register h'ffd0 tmr1 bit initial value read/write 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w clock select cks2 cks1 cks0 icks1 icks0 description 0 0 0 timer stopped 0 0 1 0 ?/8 internal clock, falling edge 0 0 1 1 ?/2 internal clock, falling edge 0 1 0 0 ?/64 internal clock, falling edge 0 1 0 1 ?/128 internal clock, falling edge 0 1 1 0 ?/1024 internal clock, falling edge 0 1 1 1 ?/2048 internal clock, falling edge 1 0 0 timer stopped 1 0 1 external clock, rising edge 1 1 0 external clock, falling edge 1 1 1 external clock, rising and falling edges tcr stcr compare-match interrupt enable a 0 compare-match a interrupt request is disabled. compare-match a interrupt request is enabled. 1 compare-match interrupt enable b 0 compare-match b interrupt request is disabled. compare-match b interrupt request is enabled. counter clear 0 0 counter is not cleared. 0 1 cleared by compare-match a. 1 0 cleared by compare-match b. 1 1 cleared on rising edge of external reset input. timer overflow interrupt enable overflow interrupt request is disabled. overflow interrupt request is enabled. 0 1 1 rev. 3.0, 09/98, page 347 of 361 tcsr ? timer control/status register h'ffd1 tmr1 bit initial value read/write 7 cmfb 0 r/(w) * 1 6 cmfa 0 r/(w) * 1 5 ovf 0 r/(w) * 1 4 1 3 os3 * 2 0 r/w 0 os0 * 2 0 r/w 2 os2 * 2 0 r/w 1 os1 * 2 0 r/w note: bit functions are the same as for tmr0. *1 *2 software can write a ??in bits 7 to 5 to clear the flags, but cannot write a ??in these bits. when all four bits (os3 to os0) are cleared to ?,?output is disabled. tcora ? time constant register a h'ffd2 tmr1 bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w note: bit functions are the same as for tmr0. tcorb ? time constant register b h'ffd3 tmr1 bit initial value read/write 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w note: bit functions are the same as for tmr0. tcnt ? timer counter h'ffd4 tmr1 bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w note: bit functions are the same as for tmr0. rev. 3.0, 09/98, page 348 of 361 smr ? serial mode register h'ffd8 sci0 bit initial value read/write 7 c/a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w 4 o/e 0 r/w clock select 0 0 1 1 1 ?clock ?4 clock 0 ?16 clock ?64 clock multiprocessor mode 0 multiprocessor function disabled 1 multiprocessor format selected stop bit length 0 one stop bit 1 two stop bits parity mode 0 even parity 1 odd parity parity enable 0 transmit: no parity bit added. receive: parity bit not checked. 1 transmit: no parity bit added. receive: parity bit not checked. character length 0 8-bit data length 1 7-bit data length communication mode 0 asynchronous 1 synchronous 3 stop 0 r/w rev. 3.0, 09/98, page 349 of 361 brr ? bit rate register h'ffd9 sci0 bit initial value read/write note: bit functions are the same as for sci1. 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w constant that determines the bit rate rev. 3.0, 09/98, page 350 of 361 scr ? serial control register h'ffda sci0 bit initial value read/write 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w clock enable 0 0 asynchronous serial clock not output asynchronous serial clock output at sck pin 1 clock enable 1 0 internal clock external clock 1 transmit end interrupt enable 0 tsr-empty interrupt request is disabled. tsr-empty interrupt request is enabled. 1 multiprocessor interrupt enable 0 multiprocessor receive interrupt function is disabled. multiprocessor receive interrupt function is enabled. 1 receive enable 0 receive disabled receive enabled 1 transmit enable 0 transmit disabled transmit enabled 1 receive interrupt enable 0 receive interrupt and receive error interrupt requests are disabled. receive interrupt and receive error interrupt requests are enabled. 1 transmit interrupt enable 0 tdr-empty interrupt request is disabled. tdr-empty interrupt request is enabled. note: bit functions are the same as for sci1. 1 rev. 3.0, 09/98, page 351 of 361 tdr ? transmit data register h'ffdb sci0 bit initial value read/write note: bit functions are the same as for sci1. 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w transmit data rev. 3.0, 09/98, page 352 of 361 ssr ? serial status register h'ffdc sci0 bit initial value read/write note: software can write a ??in bits 7 to 3 to clear the flags, but cannot write a ??in these bits. bit functions are the same as for sci1. 7 tdre 1 r/(w) 6 rdrf 0 r/(w) 5 orer 0 r/(w) 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r 4 fer 0 r/(w) receive data register full 0 cleared when cpu reads rdrf = ?,?then writes ??in rdrf. 1 set when one character is received normally and transferred from rsr to rdr. transmit data register empty 0 cleared when cpu reads tdre = ?,?then writes ??in tdre. 1 set when: 1. data is transferred from tdr to tsr. 2. te is cleared while tdre = ?. transmit end 0 cleared when cpu reads tdre = ?,?then writes ??in tdre. 1 set to ??when te = ?,?or when tdre = ??at the end of character transmission. parity error 0 cleared when cpu reads per = ?,?then writes ??in per. 1 set when a parity error occurs (parity of receive data does not match parity selected by o/e bit in smr). framing error 0 cleared when cpu reads fer = ?,?then writes ??in fer. 1 set when a framing error occurs (stop bit is ??. overrun error 0 cleared when cpu reads orer = ?,?then writes ??in orer. 1 set when an overrun error occurs (next data is completely received while rdrf bit is set to ??. multiprocessor bit multiprocessor bit transfer 0 multiprocessor bit = ??in receive data. 1 multiprocessor bit = ??in receive data. 0 multiprocessor bit = ??in transmit data. 1 multiprocessor bit = ??in transmit data. 3 per 0 r/(w) ***** rev. 3.0, 09/98, page 353 of 361 rdr ? receive data register h'ffdd sci0 bit initial value read/write note: bit functions are the same as for sci1. 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r receive data addrn ? a/d data register n (n = a, b, c, d) h'ffe0, h'ffe2, h'ffe4, h'ffe6 a/d bit initial value read/write 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r a/d conversion result rev. 3.0, 09/98, page 354 of 361 adcsr ? a/d control/status register h'ffe8 a/d bit initial value read/write 7 adf 0 r/(w)* 6 adie 0 r/w 5 adst 0 r/w 4 scan 0 r/w 3 cks 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w clock select ch2 ch1 ch0 single mode scan mode 0 0 0 an0 an0 0 1 an1 an0, an1 1 0 an2 an0 to an2 1 1 an3 an0 to an3 1 0 0 an4 an4 0 1 an5 an4, an5 1 0 an6 an4 to an6 1 1 an7 an4 to an7 a/d start 0 a/d conversion is halted. 1. 2. single mode: one a/d conversion is performed, then this bit is automatically cleared to 0. scan mode: a/d conversion starts and continues cyclically on all selected channels until 0 is written in this bit. 1 a/d end flag 0 note: software can write a 0 in bit 7 to clear the flag, but cannot write a 1 in this bit. cleared from "1" to "0" when cpu reads adf = "1," then writes "0" in adf. set to "1" at the following times: 1. 2. single mode: at the completion of a/d conversion scan mode: when all selected channels have been converted. 1 a/d interrupt enable 0 the a/d interrupt request (adi) is disabled. the a/d interrupt request (adi) is enabled. scan mode single mode scan mode 0 1 clock select conversion time = 242 states (max) conversion time = 122 states (max) 0 1 1 rev. 3.0, 09/98, page 355 of 361 adcr ? a/d control register h'ffea a/d bit initial value read/write 7 trge 0 r/w 6 1 5 1 4 1 3 1 0 chs 0 r/w 2 1 1 1 trigger enable adtrg is disabled. adtrg is enabled. a/d conversion can be started by external trigger, or by software. 0 1 reserved bit. rev. 3.0, 09/98, page 356 of 361 appendix c pin states c.1 pin states in each mode table c.1 pin states pin name mcu mode reset hardware standby software standby sleep mode normal operation 1 low 3-state low a 7 - a 0 p1 7 - p1 0 a 7 - a 0 2 3-state low if ddr = 1, prev. state if ddr = 0 prev. state (addr. output pins: last address accessed) addr. output or input port 3 prev. state i/o port 1 low 3-state low a15 - a8 p2 7 - p2 0 a1 5 - a 8 2 3-state low if ddr = 1, prev. state if ddr = 0 prev. state (addr. output pins: last address accessed) addr. output or input port 3 prev. state i/o port 1 3-state 3-state 3-state 3-state d 7 - d 0 p3 7 - p3 0 d 7 - d 0 2 3 prev. state prev. state i/o port p4 7 - p4 0 1 2 3 3-state 3-state prev. state * prev. state i/o port p5 2 - p5 0 1 2 3 3-state 3-state prev. state * prev. state i/o port notes: 1. 3-state: high-impedance state 2. prev. state: previous state. input ports are in the high-impedance state (with the mos pull-up on if pcr = 1). output ports hold their previous output level. 3. i/o port: direction depends on the data direction (ddr) bit. note that these pins may also be used by the on-chip supporting modules. see section 5, i/o ports, for further information. * on-chip supporting modules are initialized, so these pins revert to i/o ports according to the ddr and dr bits. rev. 3.0, 09/98, page 357 of 361 table c.1 pin states (cont) pin name mcu mode reset hardware standby software standby sleep mode normal operation p6 7 - p6 0 1 2 3 3-state 3-state prev. state * prev. state i/o port p7 7 - p7 0 1 2 3 3-state 3-state 3-state 3-state input port p8 6 - p8 0 1 2 3 3-state 3-state prev. state * prev. state i/o port p9 7 / wait 1 3-state 3-state 3-state 3-state wait 2 3 prev. state prev. state i/o port p96/ f 1 3-state 2 clock output high clock output clock output 3 3-state high if ddr = 1, 3-state if ddr = 0 clock output if ddr = 1, 3-state if ddr = 0 clock output if ddr = 1, input port if ddr = 0 1 high 3-state 2 high high as , wr , rd p9 5 - p9 3 , a s , w r , r d 3 3-state prev. state prev. state i/o port p9 2 - p9 0 1 3-state 3-state prev. state prev. state i/o port 2 3 notes: 1. 3-state: high-impedance state 2. prev. state: previous state. input ports are in the high-impedance state (with the mos pull-up on if pcr = 1). output ports hold their previous output level. 3. i/o port: direction depends on the data direction (ddr) bit. note that these pins may also be used by the on-chip supporting modules. see section 5, i/o ports, for further information. * on-chip supporting modules are initialized, so these pins revert to i/o ports according to the ddr and dr bits. rev. 3.0, 09/98, page 358 of 361 appendix d timing of transition to and recovery from hardware standby mode timing of transition to hardware standby mode (1) to retain ram contents when the rame bit in syscr is cleared to 0, drive the res signal low 10 system clock cycles before the stby signal goes low, as shown below. res must remain low until stby goes low (minimum delay from stby low to res high: 0 ns). stby res t 10 t 1 3 cyc t 0 ns 2 3 (2) when the rame bit in syscr is set to 1 or when it is not necessary to retain ram contents, res does not have to be driven low as in (1). timing of recovery from hardware standby mode: drive the res signal low approximately 100 ns before stby goes high. stby res t 100 ns 3 t osc rev. 3.0, 09/98, page 359 of 361 appendix e package dimensions figure e.1 shows the dimensions of the cg-84 package. figure e.2 shows the dimensions of the cp-84 package. figure e.3 shows the dimensions of the fp-80a package. 29.21 0.38 2.16 1.27 12 32 11 33 1 84 75 53 74 54 1.27 0.635 4.03 max f 8.89 hitachi code jedec eiaj weight (reference value) cg-84 8.96 g unit: mm figure e.1 package dimensions (cg-84) rev. 3.0, 09/98, page 360 of 361 1.27 *0.42 0.10 29.28 28.20 0.50 28.20 0.50 4.40 0.20 2.55 0.15 0.10 53 33 54 74 75 84 1 11 12 32 0.75 30.23 +0.12 ?.13 30.23 +0.12 ?.13 1.94 0.90 0.38 0.08 0.20 m hitachi code jedec eiaj weight (reference value) cp-84 conforms conforms 6.4 g unit: mm *dimension including the plating thickness base material dimension figure e.2 package dimensions (cp-84) rev. 3.0, 09/98, page 361 of 361 hitachi code jedec eiaj weight (reference value) fp-80a conforms 1.2 g unit: mm *dimension including the plating thickness base material dimension 60 0 ?8 0.10 0.12 m 17.2 0.3 41 61 80 1 20 40 21 17.2 0.3 *0.32 0.08 0.65 3.05 max 1.6 0.8 0.3 14 2.70 *0.17 0.05 0.10 +0.15 ?.10 0.83 0.30 0.06 0.15 0.04 figure e.3 package dimensions (fp-80a) h8/338 series hardware manual publication date: 1st edition, july 1992 3rd edition, september 1998 published by: electronic devices sales & marketing group semiconductor & integrated circuits hitachi, ltd. edited by: technical documentation group ul media co., ltd. copyright ? hitachi, ltd., 1992. all rights reserved. printed in japan. filename: colophon.doc directory: c:\winnt\profiles\aschwerm.001\desktop\h33th025d1 template: c:\program files\microsoft office\templates\umtmp5c.dot title: superh (sh) 32-bit risc mcu/mpu series subject: author: m. toyohashi keywords: comments: creation date: 07/03/98 10:10 am change number: 10 last saved on: 06/17/99 4:34 pm last saved by: kashi total editing time: 11 minutes last printed on: 01/10/00 1:10 pm as of last complete printing number of pages: 1 number of words: 8 (approx.) number of characters: 46 (approx.) |
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